OMAPL137-HT
ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013
低功耗应用处理器
查询样品:OMAPL137-HT
1低功耗应用处理器
1.1
12345
特性
•重点内容–双核片载系统(SoC)•300MHzARM926EJ-S™精简指令集(RISC)MPU
–8位溢出保护–位域提取、设定、清空–正常化，饱和，位计数–紧凑16位指令
•300MHzC674x™超长指令字(VLIW)数字信号处理器(DSP)
–TMS320C674x定点/浮点VLIWDSP内核–增强型直接内存访问控制器3(EDMA3)–128k字节RAM共享内存–2个外部存储器接口–2个外部存储器接口模块–LCD控制器–2个串行外设接口(SPI)–多媒体卡(MMC)/安全数码卡(SD)–2个主/从内部集成电路–1个主机端口接口(HPI)–具有集成型物理层(PHY)(USB1)的USB1.1开
放式主机控制器接口（OHCI）（主机）•应用范围
–工业诊断工具–测试和测量–军用声纳/雷达–医疗测量
•C674x2级高速缓存存储器架构–32K字节L1P程序RAM/高速缓存–32K字节L1D数据RAM/高速缓存–256K字节L2统一映射RAM/闪存–灵活RAM/高速缓存分区（L1和L2）–1024KBL2ROM
•增强型直接内存访问控制器3(EDMA3)：–2个传输控制器–32个独立DMA通道–8个快速DMA通道–可编程传输突发尺寸
•TMS320C674x™定点/浮点VLIWDSP内核–支持非对齐的载入-存回架构–64个通用寄存器（32位）–6个算术逻辑单元(ALU)（32/64位）功能单位•支持32位整数，SP（IEEE单精度/32位）和DP（IEEE双精度/64位）浮点•每时钟支持高达4个SP加法，每2个时钟支持4个DP加法
–专业音频–潜孔钻井业•软件支持–德州仪器(TI)数字信号处理器(DSP)/BIOS™–芯片支持库和DSP库•ARM926EJ-S核心–32位和16位(Thumb®)指令–DSP指令扩展–单周期媒介访问层(MAC)–ARM®Jazelle®技术–嵌入式ICE-RT™用于实时调试•ARM9内存架构•C674x指令集特性–此C67x+™和C64x+™ISA拓展集。
–高达3648/2736C674x每秒百万条指令(MIPS)/ 每秒百万个浮点运算(MFLOPS)–可寻址字节（8/16/32/64位数据）
1 •每周期支持多达2个浮点（SP或者DP）近似倒数或者平方根运算 –2个乘法功能单元•混合精度IEEE浮点乘法支持高达：–2SPxSP->SP每时钟–2SPxSP->DP每2个时钟–2SPxDP->DP每3个时钟–2DPxDP->DP每4个时钟•定点乘法每时钟支持2个32x32位乘法，4个16x16位乘法，或者8个8x8位乘法，和复杂乘法 –指令压缩减少代码尺寸–所有指令所需条件–模块环路 运行的硬件支持 –受保护模式运行–对于错误检测和程序重定向的额外支持 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. 2数字信号处理器(DSP)/BIOS,C67x+,C64x+,TMS320C6000,C6000aretrademarksofTexasInstruments. 3ARM926EJ-
S,嵌入式ICE-RT,ETM9,CoreSightaretrademarksofARMLimited. 4ARM,JazelleareregisteredtrademarksofARMLimited. 5WindowsisaregisteredtrademarkofMicrosoftCorporation. PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters. 版权©2012–2013,TexasInstrumentsIncorporatedEnglishDataSheet:SPRS677 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 •128k字节RAM共享内存•3.3VLVCMOSIO（除了USB接口）•2个外部存储器接口： –扩展内存接口A(EMIFA)•NOR（8/16位宽数据）•NAND（8/16位宽数据）•具有128MB地址空间的16位SDRAM –扩展内存接口B(EMIFB)•具有256MB地址空间的32位或者16位SDRAM •3个可配置16550字节UART模块：–具有调制解调器(Modem)控制信号的UART0–只在UART0上有自动流量控制信号(CTS，RTS)–16字节先进先出(FIFO)–16x或者13x过度采样选项 •LCD控制器•2个分别具有1个芯片选择的串行外设接口(SPI)•具有安全数据I/O(SDIO)的MMC/SD接口•2个主/从内部集成电路(I2CBus™)•一个具有针对高带宽的16位宽多路复用地址/数据 总线的主机端口接口(HPI)•可编程实时单元子系统(PRUSS) –2个独立可编程实时单元(PRU)内核•32位载入/存回RISC架构•每内核4K字节指令RAM•每核心512字节数据RAM•为了省电，可通过软件将PRU子系统(PRUSS)关闭 –标准电源管理机制•时钟选通•在一个单一PSC时钟选通域下的完整子系统 –专用中断控制器–专用开关中心源•具有集成型PHY(USB1)的USB1.1OHCI（主机）•具有集成型PHY(USB0)的USB2.0如影随形(OTG)：–USB2.0高速/全速客户端–USB2.0高速/全速/低速主机 –端点0（控制）–端点1，2，3，4（控制，中断，或者ISOC）Rx 和Tx•3个多通道音频串行端口： –6个时钟区域和28个串行数据引脚–支持时分复用(TDM)，I2S，和相似格式–支持动态互联网技术(DIT)(McASP2)–用于发送和接收的FIFO缓冲器•10/100Mb/s以太网MAC(EMAC)：–符合IEEE802.3标准（只支持3.3VI/O）–精简的介质无关接口(RMII)介质无关接口–管理数据I/O(MDIO)模块•具有32kHz振荡器及分离电源轨的实时时钟•温度超过125°C时晶体振荡器无效。
建议使用外部振荡器。
•1个64位通用定时器（可配置为2个32位定时器）•1个64位通用定时器/安全装置定时器（可配置为2个32位定时器）•3个增强型脉宽调制器(eHRPWM)：–含周期和频率控制的专用16位时基计数器–6个单边，6个双边对称或者3个双边不对称输 出–死区生成–高频载波的PWM斩波–可编程控制故障区输入•3个32位增强型捕捉模块(eCAP)：–可配置为3个捕捉输入或者3个辅助脉宽调制器 (APWM)输出–高达4个事件时间戳的单脉冲捕捉•2个32位增强型正交编码器脉冲模块(eQEP)•176个引脚PowerPADTM塑料四方扁平封装（PTP后缀），0.5mm引脚中心距•高温(175°C)应用•德州仪器(TI)的高温产品使用高度优化且设计和工艺提升的硅芯片解决方案以大大提高扩展温度范围内的性能。
所有器件在最大额定温度上可连续运行1000小时。
•社区资源–TIE2E社区–TI嵌入式处理器维客
2 低功耗应用处理器 版权©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 1.2商标DSP/BIOS，TMS320C6000™，C6000，TMS320，TMS320C62x，和TMS320C67x是德州仪器(TI)的商标。
所有商标均为其各自所有者所有。
版权©2012–2013,TexasInstrumentsIncorporated 低功耗应用处理器
3 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 1.3说明 OMAPL137是一款基于ARM926EJ-S和C674xDSP内核的低功率应用处理器它的功耗大大低于DSP的TMS320C6000平台上的其它产品。
OMAPL137使原设备生产商(OEM)和原设计厂商(ODM)能够快速将特有强健操作系统支持、丰富的用户接口、和在完全集成混合处理器解决方案的最大灵活性内范围内具有高处理性能的器件推向市场。
OMAPL137的双核架构提供了DSP和精简指令集计算机(RISC)技术优势，这些技术包含高性能TMS320C674xDSP内核和一个ARM926EJ-S内核。
ARM926EJ-S是32位RISC处理器内核，可执行32位或16位指令和处理32位、16位或8位数据。
该内核采用流水线结构，因此处理器和存储器系统的所有部件能够连续运作。
ARM内核具有一个协处理器15(CP15)、保护模块、和具有表格后援缓冲器的数据和程序内存管理单元(MMU)。
它具有分离的16k字节指令高速缓存和16k字节数据高速缓存。
这两种高速缓存均与虚拟索引虚拟标签(VIVT)四路关联。
另外，ARM内核还具有一个8kBRAM（矢量表）和64kBROM。
OMAPL137DSP内核使用1个两级基于闪存的架构。
1级程序高速缓存(L1P)是32kB直接映射高速缓存，而1级数据高速缓存(L1D)则为32kB两路组相关高速缓存。
2级程序高速缓存(L2P)包含一个256KB的内存空间，为程序空间和数据空间所共用。
L2内存可被配置为映射内存、高速缓存或这两者的组合。
虽然DSPL2可由ARM或系统中的其他主机进行存取，但另外还提供了供其他主机使用的128kBRAM共享内存，而不会影响DSP的性能。
外设集包括：1具有管理数据输入/输出(MDIO)模块的10/100Mb/s以太网MAC(EMAC)；2个内部集成电路(I2C)接口；3个分别具有16/12/4个串行器和FIFO缓冲器的多通道音频串口(McASP)；2个分别可进行配置的64位通用定时器（其中1个可被配置为安全装置）；1个可配置的16位主机端口接口(HPI)；高达8通道的具有可编程中断/时间生成模式的16引脚通用输入/输出(GPIO)，与其它外设复用；3个UART接口（其中一个具有RTS和CTS）；3个32位增强型捕捉(eCAP)模块外设，此外设可被配置为3个捕捉输入或者3个辅助脉宽调制器(APWM)输出；2个32位增强型正交脉冲(eQEP)外设；和2个外部存储器接口；1个用于速度较慢内存或者外设的异步和SDRAM外部存储器接口(EMIFA)，和1个用于SDRAM的较快速内存接口(EMIFB)。
以太网介质访问控制器(EMAC)在OMAP-L137和网络之间提供了1个高效端口。
EMAC支持10Base-T和100Base-TX，即半双工或全双工模式中的10M比特/秒(Mbps)和100Mbps。
此外，还为PHY配置提供了一个管理数据输入/输出(MDIO)接口。
HPI，I2C，SPI，USB1.1和USB2.0端口使得器件可以很容易地控制外设器件和/或者与主机处理器间的通信。
丰富的外设集提供了控制外围设备以及与外部处理器进行通信的能力。
如需了解每种外设的详细信息，请查阅本文件后面的有关章节以及相关联的外设参考指南。
此器件有一个用于包括此ARM和DSP的完整开发集。
这个开发集包括C编译器，1个用于简化编程和时序安排的DSP汇编优化器，和1个Windows®调试器接口，此接口用于源代码执行的可视性。
4 低功耗应用处理器 版权©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 1.4 功能方框图图1-1显示了器件的功能方框框图。
InputClock(s) SystemControl JTAGInterface PLL/ClockGenerator w/OSC GeneralPurpose Timer GeneralPurpose Timer(Watchdog) Power/SleepController RTC/ Pin 32-KHzOSC Multiplexing ARMSubsystem ARM926EJ-SCPUWithMMU 4KBETB 16KB16KBI-CacheD-Cache 8KBRAM(VectorTable) 64KBROM DSPSubsystem C674x™DSPCPU AET32KB32KBL1PgmL1RAM256KBL2RAM BOOTROM SwitchedCentralResource(SCR) PeripheralsDMA AudioPorts SerialInterfaces DisplayInternalMemory GPIO EDMA3 ControlTimers McASPw/FIFO
(3) I2C SPI UART
(2)
(2)
(3) Connectivity LCDCtlr 128KBRAM PRUSubsystem ExternalMemoryInterfaces eHRPWM
(3) eCAP
(3) eQEP
(2) USB2.0USB1.1(10/100) MMC/SDEMIFA(8b/16B) EMIFB OTGCtlrOHCICtlrEMACMDIO HPI (8b) NAND/FlashSDRAMOnly PHY PHY (RMII) 16bSDRAM (16b/32b) Note:Notallperipheralsareavailableatthesametimeduetomultiplexing. 图1-
1.OMAPL137功能方框图 版权©2012–2013,TexasInstrumentsIncorporated 低功耗应用处理器
5 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 1低功耗应用处理器........................................11.1特性..................................................11.2商标..................................................31.3说明..................................................41.4功能方框图...........................................5 2DeviceOverview........................................72.1DeviceCharacteristics...............................72.2DeviceCompatibility.................................82.3ARMSubsystem.....................................82.4DSPSubsystem....................................112.5MemoryMapSummary............................172.6BareDieInformation...............................212.7PinAssignments....................................282.8TerminalFunctions.................................29 3DeviceConfiguration.................................453.1Introduction.........................................453.2BootModesSupported.............................453.3SYSCFGModule...................................45 4DeviceOperatingConditions.......................48 4.1AbsoluteMaximumRatingsOverOperatingCaseTemperatureRange (UnlessOtherwiseNoted).................................484.2mendedOperatingConditions..............494.3ElectricalCharacteristics...........................50 5PeripheralInformationandElectrical Specifications..........................................515.1ParameterInformation..............................51 5.2mendedClockandControlSignalTransition Behavior............................................515.3PowerSupplies.....................................525.4Reset...............................................535.5CrystalOscillatororExternalClockInput..........555.6ClockPLLs.........................................565.7Interrupts............................................595.8General-PurposeInput/Output(GPIO).............675.9EDMA...............................................705.10ExternalMemoryInterfaceA(EMIFA).............755.11ExternalMemoryInterfaceB(EMIFB).............84 5.12MMC/SD/SDIO(MMCSD).......................905.13MediaessController(EMAC).........925.14ManagementDataInput/Output(MDIO)...........98 5.15MultichannelAudioSerialPorts(McASP0,McASP1, andMcASP2).....................................1005.16SerialPeripheralInterfacePorts(SPI0,SPI1)....1145.17EnhancedCaptureModule(eCAP)...............1325.18EnhancedQuadratureEncoderModule(eQEP)..135 5.19EnhancedHigh-ResolutionPulse-WidthModulator (eHRPWM)........................................1375.20LCDController....................................1405.21Timers.............................................1555.22Inter-IntegratedCircuitSerialPorts(I2C0,I2C1).157 5.23UniversalAsynchronousReceiver/Transmitter (UART)............................................1615.24USB1HostController(USB1.1OHCI)............1635.25USB0OTG(USB2.0OTG)........................1645.26UniversalHost-PortInterface(UHPI).............1725.27MemoryProtectionUnits(MPU)..................1765.28PowerandSleepController(PSC)................1785.29EmulationLogic...................................1815.30RealTimeClock(RTC)...........................1886DeviceandDocumentSupport...................1916.1DeviceSupport....................................1916.2DocumentationSupport...........................192 7MechanicalPackagingandOrderable Information............................................193 7.1DeviceandDevelopment-SupportTool Nomenclature.....................................1937.2PackagingMaterialsInformation..................1947.3ThermalDataforPTP.............................195 7.4SupplementaryInformationAboutthe176-pinPTP PowerPAD™Package............................1957.5PackagingInformation............................1967.6MechanicalDrawings.............................1967.7dMAX..............................................1987.8KeyManager......................................1987.9SECCTRL.........................................199RevisionHistory...........................................200
6 内容 SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 2DeviceOverview 2.1DeviceCharacteristics Table2-1providesanoverviewofOMAPL137.Thetableshowssignificantfeaturesofthedevice,includingthecapacityofon-chipRAM,peripherals,andthepackagetypewithpincount. Table2-
1.CharacteristicsoftheOMAPL137Processor HARDWAREFEATURESEMIFBEMIFAFlashCardInterfaceEDMA3dMAX Timers Peripherals Notallperipheralspinsareavailableatthesametime(formoredetail,seetheDeviceConfigurationssection). UART SPII2C MultichannelAudioSerialPort[McASP] 10/100MACwithManagementDataI/O eHRPWM eCAP eQEP UHPI USB2.0(USB0) USB1.1(USB1) General-PurposeInput/OutputPort LCDController RTC Size(Bytes) On-ChipMemory Organization C674xCPUID+CPURevID C674xMegamoduleRevision JTAGBSDL_ID ControlStatusRegister(CSR.[31:16]) RevisionIDRegister(MM_REVID[15:0]) DEVIDR0register CPUFrequency MHz SDRAMonly,16-bitbuswidth,upto256MbitAsynchronous(8-bitbuswidth)RAM,Flash,NOR,NAND MMCandSDcardssupported.32independentchannels,8QDMAchannels,2Transfercontrollers 16independentchannels264-BitGeneralPurpose(configurableas2separate32-bittimers,1configurableas WatchDog)3(onewithRTSandCTSflowcontrol)2(Eachwithonehardwarechipselect) 2(bothMaster/Slave) 3(eachwithtransmit/receive,FIFObuffer,16/12/4serializers) 1(RMIIInterface) 6SingleEdge,6DualEdgeSymmetric,or3DualEdgeAsymmetricOutputs332-bitcaptureinputsor332-bitauxiliaryPWMoutputs232-bitQEPchannelswith4inputs/channelFullSpeedHostOrDevicewithOn-ChipPHY- 8banksof16-bit 11(32KHzoscillatorandseperatepowertrail.Providestimeanddatetrackingandalarm capability.)488KBRAM,1088KBROM DSP32KBL1Program(L1P)/Cache(upto32KB) 32KBL1Data(L1D)/Cache(upto32KB)256KBUnifiedMappedRAM/Cache(L2) 1024KBROM(L2)DSPMemoriescanbemadeessibletoARM,EDMA3,andotherperipherals. ARM16KBI-Cache16KBD-Cache8KBRAM(VectorTable) 64KBROM ADDITIONALSHAREDMEMORY128KBRAM 0x1400 0x0000 0x8B7DF02F674xDSP300MHzARM926300MHz Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview
7 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 Table2-
1.CharacteristicsoftheOMAPL137Processor(continued) HARDWAREFEATURES CycleTime ns VoltagePackage ProductStatus
(1) Core(V)I/O(V) ProductPreview(PP),AdvanceInformation(AI),orProductionData(PD) 674xDSP3.33nsARM9263.33ns 1.2V3.3V24mmx24mm,176-Pin,0.5mmpitch,TQFP(PTP) AI
(1)ADVANCEINFORMATIONconcernsnewproductsinthesamplingorpreproductionphaseofdevelopment.Characteristicdataandotherspecificationsaresubjecttochangewithoutnotice.PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters. 2.2DeviceCompatibility TheARM926EJ-SRISCCPUpatiblewithotherARM9CPUsfromARMHoldingsplc. TheC674xDSPcoreispatiblewiththeC6000™DSPplatformandsupportsfeaturesofboththeC64x+andC67x+DSPfamilies. 2.3ARMSubsystem TheARMSubsystemincludesthefollowingfeatures:•ARM926EJ-SRISCprocessor•ARMv5TEJ(32/16-bit)instructionset•Littleendian•SystemControlCo-Processor15(CP15)•MMU•16KBInstructioncache•16KBDatacache•WriteBuffer•EmbeddedTraceModuleandEmbeddedTraceBuffer(ETM/ETB)•ARMInterruptcontroller 2.3.1ARM926EJ-SRISCCPU TheARMSubsystemintegratestheARM926EJ-Sprocessor.TheARM926EJ-SprocessorisamemberofARM9familyofgeneral-purposemicroprocessors.Thisprocessoristargetedatmulti-taskingapplicationswherefullmemorymanagement,highperformance,lowdiesize,andlowpowerareallimportant.TheARM926EJ-Sprocessorsupportsthe32-bitARMand16bitTHUMBinstructionsets,enablingtheusertotradeoffbetweenhighperformanceandhighcodedensity.Specifically,theARM926EJ-SprocessorsupportstheARMv5TEJinstructionset,whichincludesfeaturesforefficientexecutionofJavabytecodes,providingJavaperformancesimilartoJustinTime(JIT)Javainterpreter,butwithoutassociatedcodeoverhead. TheARM926EJ-SprocessorsupportstheARMdebugarchitectureandincludeslogictoassistinbothhardwareandsoftwaredebug.TheARM926EJ-SprocessorhasaHarvardarchitectureandprovidespletehighperformancesubsystem,including: •ARM926EJ-Sintegercore •CP15systemcontrolcoprocessor •MemoryManagementUnit(MMU)
8 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 •SeparateinstructionanddataCaches•Writebuffer•Separateinstructionanddata(internalRAM)interfaces•SeparateinstructionanddataAHBbusinterfaces•EmbeddedTraceModuleandEmbeddedTraceBuffer(ETM/ETB) ForpletedetailsontheARM9,refertotheARM926EJ-STechnicalReferenceManual,availableat 2.3.2CP15 TheARM926EJ-Ssystemcontrolcoprocessor(CP15)isusedtoconfigureandcontrolinstructionanddatacaches,MemoryManagementUnit(MMU),andotherARMsubsystemfunctions.TheCP15registersareprogrammedusingtheMRCandMCRARMinstructions,whentheARMinaprivilegedmodesuchassupervisororsystemmode. 2.3.3MMU Asinglesetoftwolevelpagetablesstoredinmainmemoryisusedtocontroltheaddresstranslation,permissionchecksandmemoryregionattributesforbothdataandinstructionesses.TheMMUusesasingleunifiedTranslationLookasideBuffer(TLB)tocachetheinformationheldinthepagetables.TheMMUfeaturesare:•StandardARMarchitecturev4andv5MMUmappingsizes,domainsandessprotectionscheme.•Mappingsizesare: –1MB(sections)–64KB(largepages)–4KB(smallpages)–1KB(tinypages)•esspermissionsforlargepagesandsmallpagescanbespecifiedseparatelyforeachquarterofthepage(subpagepermissions)•Hardwarepagetablewalks•InvalidateentireTLB,usingCP15register8•InvalidateTLBentry,selectedbyMVA,usingCP15register8•LockdownofTLBentries,usingCP15register10 2.3.4CachesandWriteBuffer ThesizeoftheInstructionCacheis16KB,Datacacheis16KB.Additionally,theCacheshavethefollowingfeatures: •Virtualindex,virtualtag,andaddressedusingtheModifiedVirtualAddress(MVA) •Four-waysetassociative,withacachelinelengthofeightwordsperline(32-bytesperline)andwithtwodirtybitsintheDcache •Dcachesupportswrite-throughandwrite-back(orcopyback)cacheoperation,selectedbymemoryregionusingtheCandBbitsintheMMUtranslationtables. •Critical-wordfirstcacherefilling •Cachelockdownregistersenablecontroloverwhichcachewaysareusedforallocationonalinefill,providingamechanismforbothlockdown,andcontrollingcachecorruption •DcachestoresthePhysicalAddressTAG(PATAG)correspondingtoeachDcacheentryintheTAGRAMforuseduringthecachelinewrite-backs,inadditiontotheVirtualAddressTAGstoredintheTAGRAM.ThismeansthattheMMUisnotinvolvedinDcachewrite-backoperations,removingthepossibilityofTLBmissesrelatedtothewrite-backaddress. •Cachemaintenanceoperationsprovideefficientinvalidationof,theentireDcacheorIcache,regionsoftheDcacheorIcache,andregionsofvirtualmemory. Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview
9 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 Thewritebufferisusedforallwritestoanoncachablebufferableregion,write-throughregionandwritemissestoawrite-backregion.AseparatebufferisincorporatedintheDcacheforholdingwrite-backforcachelineevictionsorcleaningofdirtycachelines.Themainwritebufferhas16-worddatabufferandafour-addressbuffer.TheDcachewrite-backhaseightdatawordentriesandasingleaddressentry. 2.3.5AdvancedHigh-PerformanceBus(AHB) TheARMSubsystemusestheAHBportoftheARM926EJ-StoconnecttheARMtotheConfigbusandtheexternalmemories.ArbitersareemployedtoarbitrateesstotheseparateD-AHBandI-AHBbytheConfigBusandtheexternalmemoriesbus. 2.3.6EmbeddedTraceMacrocell(ETM)andEmbeddedTraceBuffer(ETB) Tosupportreal-timetrace,theARM926EJ-SprocessorprovidesaninterfacetoenableconnectionofanEmbeddedTraceMacrocell(ETM).TheARM926EJ-SSubsysteminthedevicealsoincludestheEmbeddedTraceBuffer(ETB).TheETMconsistsoftwoparts:•TracePortprovidesreal-timetracecapabilityfortheARM9.•Triggeringfacilitiesprovidetriggerresources,whichincludeaddressandparators,counter, andsequencers. ThedevicetraceportisnotpinnedoutandisinsteadonlyconnectedtotheEmbeddedTraceBuffer.TheETBhasa4KBbuffermemory.ETBenableddebugtoolsarerequiredtoread/interpretthecapturedtracedata. ThisdeviceusesETM9™versionr2p2andETBversionr0p1.DocumentationontheETMandETBisavailablefromARMLtd.Referencethe'CoreSight™ETM9™TechnicalReferenceManual,revisionr0p1'andthe'ETM9TechnicalReferenceManual,revisionr2p2'. 2.3.7ARMMemoryMapping BydefaulttheARMhasesstomostonandoffchipmemoryareas,includingtheDSPInternalmemories,EMIFA,EMIFB,andtheadditional128KbyteonchipsharedSRAM.LikewisealmostalloftheonchipperipheralsareessibletotheARMbydefault. Toimprovesecurityand/orrobustnessthedevicehasextensivememoryandperipheralprotectionunitswhichcanbeconfiguredtolimitessrightstothevariouson/offchipresourcestospecifichosts;includingtheARMaswellasothermasterperipherals.ThisallowsthesystemtaskstobepartitionedbetweentheARMandDSPasbestsuitestheparticularapplication;whileenhancingtheoverallrobustnessofthesolution. SeeTable2-3foralevelOMAPL137memorymapthatincludestheARMmemoryspace. 10 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated 2.4DSPSubsystem TheDSPSubsystemincludesthefollowingfeatures:•C674xDSPCPU•32KBL1Program(L1P)/Cache(upto32KB)•32KBL1Data(L1D)/Cache(upto32KB)•256KBUnifiedMappedRAM/Cache(L2)•1MBMask-programmableROM•Littleendian OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 32KBytesL1PRAM/ Cache 256 256KBytesL2RAM 256 BootROM256 256CacheControlMemoryProtectL1PBandwidthMgmt CacheControlMemoryProtectL2BandwidthMgmt 256 256 InstructionFetch C674xFixed/FloatingPointCPU RegisterFileA 64 RegisterFileB 64 256 IDMA256 256 PowerDown InterruptController BandwidthMgmtMemoryProtectL1DCacheControl EMC CFG MDMA SDMA 8x32 64 6464 64 32KBytesL1DRAM/ Cache HighPerformanceSwitchFabric 32ConfigurationPeripheralsBus Figure2-
1.C674xMegamoduleBlockDiagram Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview 11 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 2.4.1C674xDSPCPUDescription TheC674xCentralProcessingUnit(CPU)consistsofeightfunctionalunits,tworegisterfiles,andtwodatapathsasshowninFigure2-
2.Thetwogeneral-purposeregisterfiles(AandB)eachcontain3232bitregistersforatotalof64registers.Thegeneral-purposeregisterscanbeusedfordataorcanbedataaddresspointers.Thedatatypessupportedincludepacked8-bitdata,packed16-bitdata,32-bitdata,40bitdata,and64-bitdata.Valueslargerthan32bits,suchas40-bit-longor64-bit-longvaluesarestoredinregisterpairs,withthe32LSBsofdataplacedinanevenregisterandtheremaining8or32MSBsinthenextupperregister(whichisalwaysanodd-numberedregister). Theeightfunctionalunits(.M1,.L1,.D1,.S1,.M2,.L2,.D2,and.S2)areeachcapableofexecutingoneinstructioneveryclockcycle.The.Mfunctionalunitsperformallmultiplyoperations.The.Sand.Lunitsperformageneralsetofarithmetic,logical,andbranchfunctions.The.Dunitsprimarilyloaddatafrommemorytotheregisterfileandstoreresultsfromtheregisterfileintomemory. TheC674xbinestheperformanceoftheC64x+corewiththefloating-pointcapabilitiesoftheC67xcore. EachC674x.Munitcanperformoneofthefollowingeachclockcycle:one32x32bitmultiply,one16x32bitmultiply,two16x16bitmultiplies,two16x32bitmultiplies,two16x16bitmultiplieswithadd/subtractcapabilities,four8x8bitmultiplies,four8x8bitmultiplieswithaddoperations,andfour16x16multiplieswithadd/subtractcapabilities(includingplexmultiply).ThereisalsosupportforGaloisfieldmultiplicationfor8-bitand32-bitdata.municationsalgorithmssuchasFFTsandmodemsplexmultiplication.plexmultiply(CMPY)instructiontakesfour16-bitinputsandproducesa32-bitrealanda32-bitimaginaryoutput.Thereareplexmultiplieswithroundingcapabilitythatproducesone32-bitpackedoutputthatcontain16-bitrealand16-bitimaginaryvalues.The32x32bitmultiplyinstructionsprovidetheextendedprecisionnecessaryforaudioandotherhighprecisionalgorithmsonavarietyofsignedandunsigned32-bitdatatypes. The.Lor(ArithmeticLogicUnit)nowincorporatestheabilitytodoparalleladd/subtractoperationsonapairmoninputs.Versionsofthisinstructionexisttoworkon32-bitdataoronpairsof16-bitdataperformingdual16-bitaddandsubtractsinparallel.Therearealsosaturatedformsoftheseinstructions. TheC674xcoreenhancesthe.Sunitinseveralways.Onpreviouscores,dual16-bitMIN2andparisonswereonlyavailableonthe.Lunits.OntheC674xcoretheyarealsoavailableonthe.Sunitwhichincreasestheperformanceofalgorithmsthatdosearchingandsorting.Finally,toincreasedatapackingandunpackingthroughput,the.Sunitallowssustainedhighperformanceforthequad8-bit/16-bitanddual16-bitinstructions.Unpackinstructionsprepare8-bitdataforparallel16-bitoperations.Packinstructionsreturnparallelresultstooutputprecisionincludingsaturationsupport. Othernewfeaturesinclude: •SPLOOP-AsmallinstructionbufferintheCPUthataidsincreationofsoftwarepipeliningloopswheremultipleiterationsofaloopareexecutedinparallel.TheSPLOOPbufferreducesthecodesizeassociatedwithsoftwarepipelining.Furthermore,loopsintheSPLOOPbufferarefullyinterruptible. •CompactInstructions-ThenativeinstructionsizefortheC6000devicesis32bits.moninstructionssuchasMPY,AND,OR,ADD,andSUBcanbeexpressedas16bitsifthepilercanrestrictthecodetousecertainregistersintheregisterfile.pressionisperformedbythecodegenerationtools. •InstructionSetEnhancement-Asnotedabove,therearenewinstructionssuchas32-bitmultiplications,plexmultiplications,packing,sorting,bitmanipulation,and32-bitGaloisfieldmultiplication. •ExceptionsHandling-Intendedtoaidtheprogrammerinisolatingbugs.TheC674xCPUisabletodetectandrespondtoexceptions,bothfrominternallydetectedsources(suchasillegalop-codes)andfromsystemevents(suchasawatchdogtimeexpiration). •Privilege-Definesuserandsupervisormodesofoperation,allowingtheoperatingsystemtogiveabasiclevelofprotectiontosensitiveresources.Localmemoryisdividedintomultiplepages,eachwithread,write,andexecutepermissions. 12 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 •Time-StampCounter-PrimarilytargetedforReal-TimeOperatingSystem(RTOS)robustness,afreerunningtime-stampcounterisimplementedintheCPUwhichisnotsensitivetosystemstalls. FormoredetailsontheC674xCPUanditsenhancementsovertheC64xarchitecture,seethefollowingdocuments:•TMS320C64x/C64x+DSPCPUandInstructionSetReferenceGuide(literaturenumberSPRU732)•TMS320C64xTechnicalOverview(literaturenumberSPRU395) Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview 13 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 DatapathA ST1bST1a 32MSB32LSB LD1bLD1a 32MSB32LSB DA1 DA2 LD2aLD2b 32LSB32MSB DatapathB ST2aST2b 32MSB32LSB src1 .L1src2 odddst evendst longsrc
8 longsrcevendstodddst.S1src1 src2 dst2dst1.M1src1src2 8 3232 dst.D1src1 src2 src2.D2src1 dst src2 .M2src1 dst2 32 dst1 32 src2 src1 .S2odddst evendst longsrc
8 Oddregister fileA(A1,A3,A5...A31) (D) Evenregister fileA(A0,A2,A4...A30) (D) (A)(B)(C) 2x 1xOdd registerfileB (B1,B3,B5...B31) Evenregister fileB(B0,B2,B4...B30) (C) (B)(A) (D) 8longsrcevendst (D) odddst.L2 src2 src1 ControlRegister Figure2-
2.TMS320C674x™CPU(DSPCore)DataPaths 2.4.2DSPMemoryMappingTheDSPmemorymapisshowninSection2.5 14 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 BydefaulttheDSPalsohasesstomostonandoffchipmemoryareas,withtheexceptionoftheARMRAM,ROM,andAINTCinterruptcontroller.TheDSPalsobootsfirst,andmustreleasetheARMfromresetbeforetheARMcanexecuteanycode. Additionally,theDSPmegamoduleincludesthecapabilitytolimitesstoitsinternalmemoriesthroughitsSDMAport;withoutneedinganexternalMPUunit. 2.4.2.1ARMInternalMemoriesTheDSPdoesnothaveesstotheARMinternalmemory. 2.4.2.2ExternalMemories TheDSPhasesstothefollowingExternalmemories:•AsynchronousEMIF/SDRAM/NAND/NORFlash(EMIFA)•SDRAM(EMIFB) 2.4.2.3DSPInternalMemories TheDSPhasesstothefollowingDSPmemories:•L2RAM•L1PRAM•L1DRAM 2.4.2.4C674xCPU TheC674xcoreusesatwo-levelcache-basedarchitecture.TheLevel1Programcache(L1P)is32KBdirectmappedcacheandtheLevel1Datacache(L1D)is32KB2-waysetassociatedcache.TheLevel2memory/cache(L2)consistsofa256KBmemoryspacethatissharedbetweenprogramanddataspace.L2memorycanbeconfiguredasmappedmemory,cache,orbinationofboth. Table2-2showsamemorymapoftheC674xCPUcacheregistersforthedevice. HEXADDRESSRANGE0x018400000x018400200x018400240x018400400x01840044 0x01840048-0x01840FFC0x01841000 0x01841004-0x01841FFC0x018420000x018420040x018420080x0184200C 0x01842010-0x01843FFF0x018440000x018440040x018440100x018440140x018440180x0184401C0x01844020 Table2-
2.C674xCacheRegisters REGISTERACRONYML2CFGL1PCFGL1PCCL1DCFGL1DCC- EDMAWEIGHT- L2ALLOC0L2ALLOC1L2ALLOC2L2ALLOC3 L2WBARL2WWCL2WIBARL2WIWCL2IBAR L2IWCL1PIBAR DESCRIPTIONL2CacheconfigurationregisterL1PSizeCacheconfigurationregisterL1PFreezeModeCacheconfigurationregisterL1DSizeCacheconfigurationregisterL1DFreezeModeCacheconfigurationregisterReservedL2EDMAesscontrolregisterReservedL2allocationregister0L2allocationregister1L2allocationregister2L2allocationregister3ReservedL2writebackbaseaddressregisterL2writebackwordcountregisterL2writebackinvalidatebaseaddressregisterL2writebackinvalidatewordcountregisterL2invalidatebaseaddressregisterL2invalidatewordcountregisterL1Pinvalidatebaseaddressregister Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview 15 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 HEXADDRESSRANGE0x018440240x018440300x018440340x018440380x018440400x018440440x018440480x0184404C 0x01844050-0x01844FFF0x018450000x018450040x01845008 0x0184500C-0x018450270x01845028 0x0184502C-0x018450390x018450400x018450440x01845048 0x01848000–0x018480FF 0x01848100–0x0184817F 0x01848180–0x01848187 0x01848188–0x0184818F 0x01848190–0x01848197 0x01848198–0x0184819F 0x018481A0–0x018481FF 0x01848200 0x01848204–0x018482FF 0x01848300–0x0184837F 0x01848380–0x018483FF Table2-
2.C674xCacheRegisters(continued) REGISTERACRONYML1PIWC L1DWIBARL1DWIWC L1DWBARL1DWWCL1DIBAR L1DIWC- L2WBL2WBINV L2INV- L1PINV- L1DWBL1DWBINV L1DINVMAR0-MAR63 MAR64–MAR95 MAR96-MAR97 MAR98–MAR99 MAR100–MAR101 MAR102–MAR103 MAR104–MAR127 MAR128 MAR129–MAR191 MAR192–MAR223 MAR224–MAR255 DESCRIPTIONL1PinvalidatewordcountregisterL1DwritebackinvalidatebaseaddressregisterL1DwritebackinvalidatewordcountregisterReservedL1DBlockWritebackL1DBlockWritebackL1DinvalidatebaseaddressregisterL1DinvalidatewordcountregisterReservedL2writebackallregisterL2writebackinvalidateallregisterL2GlobalInvalidatewithoutwritebackReservedL1PGlobalInvalidateReservedL1DGlobalWritebackL1DGlobalWritebackwithInvalidateL1DGlobalInvalidatewithoutwritebackReserved0x00000000–0x3FFFFFFFMemoryAttributeRegistersforEMIFASDRAMData(CS0)0x40000000–0x5FFFFFFFMemoryAttributeRegistersforEMIFAAsyncData(CS2)0x60000000–0x61FFFFFFMemoryAttributeRegistersforEMIFAAsyncData(CS2)0x62000000–0x63FFFFFFMemoryAttributeRegistersforEMIFAAsyncData(CS2)0x64000000–0x65FFFFFFMemoryAttributeRegistersforEMIFAAsyncData(CS2)0x66000000–0x67FFFFFFReserved0x68000000–0x7FFFFFFFMemoryAttributeRegisterforSharedRAM0x80000000–0x8001FFFFReserved0x80020000–0x81FFFFFFReserved0x82000000–0xBFFFFFFFMemoryAttributeRegistersforEMIFDSDRAMData(CS2)0xC0000000–0xDFFFFFFFReserved0xE0000000–0xFFFFFFFF SeeTable2-3foralevelOMAPL137memorymapthatincludestheDSPmemoryspace. 16 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 2.5MemoryMapSummary StartAddress 0x00000000 0x00001000 0x007000000x008000000x00840000 0x00E000000x00E080000x00F000000x00F08000 0x01800000 0x01810000 0x018110000x018120000x018130000x018200000x01830000 0x01840000 0x018500000x01880000 0x01BC04000x01BC04300x01BC0000 0x01BC10000x01BC1800 0x01BC0500 0x01BD00000x01BE00000x01C000000x01C080000x01C084000x01C088000x01C100000x01C110000x01C120000x01C14000 EndAddress 0x00000FFF 0x006FFFFF 0x007FFFFF0x0083FFFF0x00DFFFFF 0x00E07FFF0x00EFFFFF0x00F07FFF0x017FFFFF 0x0180FFFF 0x01810FFF 0x01811FFF0x01812FFF0x0181FFFF0x0182FFFF0x0183FFFF 0x0184FFFF 0x0187FFFF0x01BC03FF 0x01BC042F0x01BC044F0x01BC0FFF 0x01BC17FF0x01BC18FF 0x01BCFFFF 0x01BDFFFF0x01BFFFFF0x01C07FFF0x01C083FF0x01C087FF0x01C0FFFF0x01C10FFF0x01C11FFF0x01C13FFF0x01C14FFF Table2-
3.OMAPL137TopLevelMemoryMap Size ARMMemDSPMemMapEDMAMemdMAXMem Map Map Map 4K - 6M+1020K1024K256K5M+768K 32K992K32K8M+992K64K 4K 4K4K52K64K64K 64K 192K3M+257K 48324K 2K256 62K+76864K128K32K1024102430K4K4K8K4K - - - - ARMETBmemoryARMETBregARMIceCrusher - DSPL2ROMDSPL2RAM - DSPL1PRAM- DSPL1DRAM- DSPInterruptController DSPPowerdownController DSPSecurityIDDSPRevisionID DSPEMCDSPInternalReservedDSPMemory System- - - EDMA3CCEDMA3TC0EDMA3TC1PSC0PLLControllerSYSCFG dMAXLocalAddressSpace - - - - MasterPeripheralMemMap - LCDCMemMap - Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview 17 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 StartAddress 0x01C150000x01C160000x01C170000x01C180000x01C200000x01C210000x01C220000x01C230000x01C240000x01C250000x01C300000x01C30200 0x01C320000x01C32200 0x01C340000x01C380000x01C390000x01C3C0000x01C3D0000x01C400000x01C410000x01C420000x01C430000x01C440000x01D000000x01D010000x01D020000x01D030000x01D040000x01D050000x01D060000x01D070000x01D080000x01D090000x01D0A0000x01D0B0000x01D0C0000x01D0D0000x01D0E0000x01D0F0000x01E000000x01E100000x01E110000x01E12000 Table2-
3.OMAPL137TopLevelMemoryMap(continued) EndAddressSize ARMMemMap DSPMemMap EDMAMemMap dMAXMemMap 0x01C15FFF0x01C16FFF0x01C17FFF0x01C1FFFF0x01C20FFF0x01C21FFF0x01C22FFF0x01C23FFF0x01C24FFF0x01C2FFFF0x01C301FF0x01C31FFF 0x01C321FF0x01C33FFF 0x01C37FFF0x01C38FFF0x01C3BFFF0x01C3CFFF0x01C3FFFF0x01C40FFF0x01C41FFF0x01C42FFF0x01C43FFF0x01CFFFFF0x01D00FFF0x01D01FFF0x01D02FFF0x01D03FFF0x01D04FFF0x01D05FFF0x01D06FFF0x01D07FFF0x01D08FFF0x01D09FFF0x01D0AFFF0x01D0BFFF0x01D0CFFF0x01D0DFFF0x01D0EFFF0x01DFFFFF0x01E0FFFF0x01E10FFF0x01E11FFF0x01E12FFF 4K4K4K32K4K4K4K4K4K44K5127K+5125127K+51216K4K12K4K12K4K4K4K4K752K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K964K64K4K4K4K Timer64P0Timer64P1I2C0RTCdMAXDataRAM0- dMAXDataRAM1- dMAXControlRegistersdMAXMAX0ConfigurationMemory dMAXMAX1ConfigurationMemory MMC/SD0 SPI0UART0 McASP0ControlMcASP0AFIFOCtrlMcASP0DataMcASP1ControlMcASP1AFIFOCtrlMcASP1DataMcASP2ControlMcASP2AFIFOCtrlMcASP2DataUART1UART2USB0UHPISPI1 MasterPeripheralMemMap LCDCMemMap - - - - - - - - - - - - 18 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 StartAddress 0x01E130000x01E140000x01E150000x01E160000x01E200000x01E220000x01E230000x01E240000x01E250000x01E260000x01E270000x01E280000x01E290000x01E2A0000x01F000000x01F010000x01F020000x01F030000x01F040000x01F050000x01F060000x01F070000x01F080000x01F090000x01F0A0000x01F0B0000x01F0C000 0x117000000x118000000x11840000 0x11E000000x11E080000x11F000000x11F08000 0x400000000x600000000x620000000x640000000x660000000x680000000x68008000 0x80000000 Table2-
3.OMAPL137TopLevelMemoryMap(continued) EndAddressSize ARMMemMap DSPMemMap EDMAMemMap dMAXMemMap 0x01E13FFF0x01E14FFF0x01E15FFF0x01E1FFFF0x01E21FFF0x01E22FFF0x01E23FFF0x01E24FFF0x01E25FFF0x01E26FFF0x01E27FFF0x01E28FFF0x01E29FFF0x01EFFFFF0x01F00FFF0x01F01FFF0x01F02FFF0x01F03FFF0x01F04FFF0x01F05FFF0x01F06FFF0x01F07FFF0x01F08FFF0x01F09FFF0x01F0AFFF0x01F0BFFF0x116FFFFF 0x117FFFFF0x1183FFFF0x11DFFFFF 0x11E07FFF0x11EFFFFF0x11F07FFF0x3FFFFFFF 0x5FFFFFFF0x61FFFFFF0x63FFFFFF0x65FFFFFF0x67FFFFFF0x68007FFF0x7FFFFFFF 0x8001FFFF 4K4K4K40K8K4K4K4K4K4K4K4K4K856K4K4K4K4K4K4K4K4K4K4K4K4K247M+976K1024K256K5M+768K32K992K32K736M+992K512M32M32M32M32M32K383M+992K128K LCDControllerMPU1MPU2- EMACControlModuleRAMEMACControlModuleRegisters EMACControlRegistersEMACMDIOportUSB1GPIOPSC1I2C1EPWM0HRPWM0eHRPWM1HRPWM1eHRPWM2HRPWM2ECAP0ECAP1ECAP2EQEP0EQEP1- DSPL2ROMDSPL2RAM - DSPL1PRAM- DSPL1DRAM- EMIFASDRAMdata(CS0)EMIFAasyncdata(CS2)EMIFAasyncdata(CS3)EMIFAasyncdata(CS4)EMIFAasyncdata(CS5) EMIFAControlRegs- SharedRAM MasterPeripheralMemMap LCDCMemMap - - - - - - - - Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview 19 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 StartAddress 0x800200000xB00000000xB00080000xC00000000xE00000000xFFFD00000xFFFE00000xFFFEE0000xFFFF00000xFFFF2000 Table2-
3.OMAPL137TopLevelMemoryMap(continued) EndAddressSize ARMMemMap DSPMemMap EDMAMemMap dMAXMemMap 0xAFFFFFFF 0xB0007FFF0xBFFFFFFF 0xDFFFFFFF0xFFFCFFFF 0xFFFDFFFF 0xFFFEDFFF0xFFFEFFFF 0xFFFF1FFF 0xFFFFFFFF 767M+896K32K 255M+992K512M 511M+832K64K 56K8K 8K 56K ARMlocalROM ARMInterruptControllerARMlocalRAM - EMIFBControlRegs- EMIFBSDRAMData- - - - - MasterPeripheralMemMap TheDSPL2ROMisusedforbootpurposesandcannotbeprogrammedwithapplicationcode. LCDCMemMap 20 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated 2.6BareDieInformation DIETHICKNESS BACKSIDEFINISH 380µm Siliconwithbackgrind OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 BACKSIDEPOTENTIAL Floating BONDPADMETALLIZATIONCOMPOSITION TaN/AlCu BONDPADTHICKNESS 1000nm Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview 21 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 DESCRIPTIONAXR1_00UART0_RXDUART0_TXDAXR1_10VDDSHVN/CVSSAXR1_11SPI0_SCSNVDDSPI0_CLKSPI0_ENANSPI1_SOMISPI1_SIMOVDDSHVVSSN/CSPI1_CLKSPI0_SOMISPI0_SIMOEMA_WAITVDDEMA_OENEMA_CSN_2VDDSHVN/CVSSN/CN/CEMA_BA_1EMA_A_10VDDEMA_A_00EMA_A_01EMA_A_02EMA_A_03VDDSHVVSSN/CEMA_A_04EMA_A_05EMA_A_06EMA_A_07VDDEMA_A_08EMA_A_09EMA_A_11 Table2-
4.BondPadCoordinatesinMicrons PADNUMBER1234567891011121314151617181920212223242526272829303132333435363738394041424344454647 XMIN209.005279.005349.005419.005509.005582.755652.755722.755792.755862.755932.7551002.7551072.7551142.7551212.7551299.0051372.7551442.7551512.7551582.7551652.7551722.7551792.7551862.7551932.7552002.7552089.0052159.0052229.0052299.0052369.0052439.0052509.0052579.0052649.0052719.0052789.0052879.0052954.0053024.0053094.0053164.0053234.0053304.0053374.0053444.0053514.005 YMIN13.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.225 XMAX274.005344.005414.005484.005574.005647.755717.755787.755857.755927.755997.7551067.7551137.7551207.7551277.7551364.0051437.7551507.7551577.7551647.7551717.7551787.7551857.7551927.7551997.7552067.7552154.0052224.0052294.0052364.0052434.0052504.0052574.0052644.0052714.0052784.0052854.0052944.0053019.0053089.0053159.0053229.0053299.0053369.0053439.0053509.0053579.005 YMAX78.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.225 22 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT DESCRIPTIONEMA_A_12N/CVDDSHVN/CN/CN/CN/CVSSN/CEMA_D_00N/CEMA_D_01EMA_D_02N/CN/CVDDSHVN/CVSSEMA_D_03N/CEMA_D_04N/CVDDN/CEMA_D_05N/CEMA_D_06N/CVSSVDDSHVN/CN/CN/CEMA_D_07N/CEMA_WENN/CVDDVSSN/CVDDSHVVDDSHVVDDVDDN/CVSSN/C ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 Table2-
4.BondPadCoordinatesinMicrons(continued) PADNUMBER4849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394 XMIN3584.0053654.0053739.0053814.0053884.0053954.0054024.0054094.0054284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.785 YMIN13.22513.22513.22513.22513.22513.22513.22513.225209.005279.435349.865420.295510.725580.91650.91720.91790.91860.91930.911000.911070.911140.911210.911280.911355.8851444.971514.971584.971654.971724.971794.971864.971934.972004.972074.972150.6152235.3452305.3452375.3452445.3452515.3452585.3452655.3452725.3452795.3452865.3452935.345 XMAX3649.0053719.0053804.0053879.0053949.0054019.0054089.0054159.0054349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.785 YMAX78.22578.22578.22578.22578.22578.22578.22578.225274.005344.435414.865485.295575.725645.91715.91785.91855.91925.91995.911065.911135.911205.911275.911345.911420.8851509.971579.971649.971719.971789.971859.971929.971999.972069.972139.972215.6152300.3452370.3452440.3452510.3452580.3452650.3452720.3452790.3452860.3452930.3453000.345 Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview 23 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 DESCRIPTIONVDDSHVVDDAR1N/CN/CVDDNWA1VDDNWA1VDDVSSVDDSHVN/CN/CVSSN/CVDDSHVVDDN/CN/CVSSN/CVDDSHVVSSN/CN/CVDDSHVVSSVDDSHVVDDN/CVSSVDDSHVVDDVSSVDDSHVAXR0_00N/CAXR0_01AXR0_02VDDN/CN/CN/CN/CN/CAXR0_03N/CAXR0_05AXR0_06 Table2-
4.BondPadCoordinatesinMicrons(continued) PADNUMBER9596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141 XMIN4284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854090.7654020.5553949.2153878.8853808.4153738.313663.7353588.513518.4153447.745 YMIN3015.7753106.2053176.6353247.0653325.9253400.023470.023540.023610.023680.023750.023824.2253913.463983.464053.464123.464193.464263.464333.464407.6654497.344567.344637.344707.344777.344847.344917.344987.345061.5355150.3455220.3455290.3455360.3455430.3455500.3455574.5455665.4455861.2255861.2255861.2255861.2255861.2255861.2255861.2255861.2255861.2255861.225 XMAX4349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854155.7654085.5554014.2153943.8853873.4153803.313728.7353653.513583.4153512.745 YMAX3080.7753171.2053241.6353312.0653390.9253465.023535.023605.023675.023745.023815.023889.2253978.464048.464118.464188.464258.464328.464398.464472.6654562.344632.344702.344772.344842.344912.344982.345052.345126.5355215.3455285.3455355.3455425.3455495.3455565.3455639.5455730.4455926.2255926.2255926.2255926.2255926.2255926.2255926.2255926.2255926.2255926.225 24 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT DESCRIPTIONVSSVDDSHVAXR0_07AXR0_08AFSX0VDDSHVN/CVSSAHCLKR0AFSR0VPPVPPIFORCEVSENSEVDDA18V_USB1VSSUSB1_DPN/CUSB1_DMVDDA33_USB1VDDVSSUSB0_IDUSB0_VBUSVDDA12_USB0VDDA18_USB0VSSA_USB0USB0_DPN/CUSB0_DMVSSA33_USB0VDDA33_USB0VSSVDDA12_PLLVSSA12_PLLOSCINOSCVSSRESETNVDDN/CRTC_XIRTC_VSSRTC_XOVDD2N/CTRSTNTRSTN ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 Table2-
4.BondPadCoordinatesinMicrons(continued) PADNUMBER142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188 XMIN3376.0353304.273233.6453163.253089.8753019.1152948.6252869.3952798.8352726.122652.812581.052510.132439.422369.1552298.6852228.452158.2752087.535200
–高达3648/2736C674x每秒百万条指令(MIPS)/ 每秒百万个浮点运算(MFLOPS)–可寻址字节（8/16/32/64位数据）
1 •每周期支持多达2个浮点（SP或者DP）近似倒数或者平方根运算 –2个乘法功能单元•混合精度IEEE浮点乘法支持高达：–2SPxSP->SP每时钟–2SPxSP->DP每2个时钟–2SPxDP->DP每3个时钟–2DPxDP->DP每4个时钟•定点乘法每时钟支持2个32x32位乘法，4个16x16位乘法，或者8个8x8位乘法，和复杂乘法 –指令压缩减少代码尺寸–所有指令所需条件–模块环路 运行的硬件支持 –受保护模式运行–对于错误检测和程序重定向的额外支持 Pleasebeawarethatanimportantnoticeconcerningavailability,standardwarranty,anduseincriticalapplicationsofTexasInstrumentssemiconductorproductsanddisclaimerstheretoappearsattheendofthisdatasheet. 2数字信号处理器(DSP)/BIOS,C67x+,C64x+,TMS320C6000,C6000aretrademarksofTexasInstruments. 3ARM926EJ-
S,嵌入式ICE-RT,ETM9,CoreSightaretrademarksofARMLimited. 4ARM,JazelleareregisteredtrademarksofARMLimited. 5WindowsisaregisteredtrademarkofMicrosoftCorporation. PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters. 版权©2012–2013,TexasInstrumentsIncorporatedEnglishDataSheet:SPRS677 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 •128k字节RAM共享内存•3.3VLVCMOSIO（除了USB接口）•2个外部存储器接口： –扩展内存接口A(EMIFA)•NOR（8/16位宽数据）•NAND（8/16位宽数据）•具有128MB地址空间的16位SDRAM –扩展内存接口B(EMIFB)•具有256MB地址空间的32位或者16位SDRAM •3个可配置16550字节UART模块：–具有调制解调器(Modem)控制信号的UART0–只在UART0上有自动流量控制信号(CTS，RTS)–16字节先进先出(FIFO)–16x或者13x过度采样选项 •LCD控制器•2个分别具有1个芯片选择的串行外设接口(SPI)•具有安全数据I/O(SDIO)的MMC/SD接口•2个主/从内部集成电路(I2CBus™)•一个具有针对高带宽的16位宽多路复用地址/数据 总线的主机端口接口(HPI)•可编程实时单元子系统(PRUSS) –2个独立可编程实时单元(PRU)内核•32位载入/存回RISC架构•每内核4K字节指令RAM•每核心512字节数据RAM•为了省电，可通过软件将PRU子系统(PRUSS)关闭 –标准电源管理机制•时钟选通•在一个单一PSC时钟选通域下的完整子系统 –专用中断控制器–专用开关中心源•具有集成型PHY(USB1)的USB1.1OHCI（主机）•具有集成型PHY(USB0)的USB2.0如影随形(OTG)：–USB2.0高速/全速客户端–USB2.0高速/全速/低速主机 –端点0（控制）–端点1，2，3，4（控制，中断，或者ISOC）Rx 和Tx•3个多通道音频串行端口： –6个时钟区域和28个串行数据引脚–支持时分复用(TDM)，I2S，和相似格式–支持动态互联网技术(DIT)(McASP2)–用于发送和接收的FIFO缓冲器•10/100Mb/s以太网MAC(EMAC)：–符合IEEE802.3标准（只支持3.3VI/O）–精简的介质无关接口(RMII)介质无关接口–管理数据I/O(MDIO)模块•具有32kHz振荡器及分离电源轨的实时时钟•温度超过125°C时晶体振荡器无效。
建议使用外部振荡器。
•1个64位通用定时器（可配置为2个32位定时器）•1个64位通用定时器/安全装置定时器（可配置为2个32位定时器）•3个增强型脉宽调制器(eHRPWM)：–含周期和频率控制的专用16位时基计数器–6个单边，6个双边对称或者3个双边不对称输 出–死区生成–高频载波的PWM斩波–可编程控制故障区输入•3个32位增强型捕捉模块(eCAP)：–可配置为3个捕捉输入或者3个辅助脉宽调制器 (APWM)输出–高达4个事件时间戳的单脉冲捕捉•2个32位增强型正交编码器脉冲模块(eQEP)•176个引脚PowerPADTM塑料四方扁平封装（PTP后缀），0.5mm引脚中心距•高温(175°C)应用•德州仪器(TI)的高温产品使用高度优化且设计和工艺提升的硅芯片解决方案以大大提高扩展温度范围内的性能。
所有器件在最大额定温度上可连续运行1000小时。
•社区资源–TIE2E社区–TI嵌入式处理器维客
2 低功耗应用处理器 版权©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 1.2商标DSP/BIOS，TMS320C6000™，C6000，TMS320，TMS320C62x，和TMS320C67x是德州仪器(TI)的商标。
所有商标均为其各自所有者所有。
版权©2012–2013,TexasInstrumentsIncorporated 低功耗应用处理器
3 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 1.3说明 OMAPL137是一款基于ARM926EJ-S和C674xDSP内核的低功率应用处理器它的功耗大大低于DSP的TMS320C6000平台上的其它产品。
OMAPL137使原设备生产商(OEM)和原设计厂商(ODM)能够快速将特有强健操作系统支持、丰富的用户接口、和在完全集成混合处理器解决方案的最大灵活性内范围内具有高处理性能的器件推向市场。
OMAPL137的双核架构提供了DSP和精简指令集计算机(RISC)技术优势，这些技术包含高性能TMS320C674xDSP内核和一个ARM926EJ-S内核。
ARM926EJ-S是32位RISC处理器内核，可执行32位或16位指令和处理32位、16位或8位数据。
该内核采用流水线结构，因此处理器和存储器系统的所有部件能够连续运作。
ARM内核具有一个协处理器15(CP15)、保护模块、和具有表格后援缓冲器的数据和程序内存管理单元(MMU)。
它具有分离的16k字节指令高速缓存和16k字节数据高速缓存。
这两种高速缓存均与虚拟索引虚拟标签(VIVT)四路关联。
另外，ARM内核还具有一个8kBRAM（矢量表）和64kBROM。
OMAPL137DSP内核使用1个两级基于闪存的架构。
1级程序高速缓存(L1P)是32kB直接映射高速缓存，而1级数据高速缓存(L1D)则为32kB两路组相关高速缓存。
2级程序高速缓存(L2P)包含一个256KB的内存空间，为程序空间和数据空间所共用。
L2内存可被配置为映射内存、高速缓存或这两者的组合。
虽然DSPL2可由ARM或系统中的其他主机进行存取，但另外还提供了供其他主机使用的128kBRAM共享内存，而不会影响DSP的性能。
外设集包括：1具有管理数据输入/输出(MDIO)模块的10/100Mb/s以太网MAC(EMAC)；2个内部集成电路(I2C)接口；3个分别具有16/12/4个串行器和FIFO缓冲器的多通道音频串口(McASP)；2个分别可进行配置的64位通用定时器（其中1个可被配置为安全装置）；1个可配置的16位主机端口接口(HPI)；高达8通道的具有可编程中断/时间生成模式的16引脚通用输入/输出(GPIO)，与其它外设复用；3个UART接口（其中一个具有RTS和CTS）；3个32位增强型捕捉(eCAP)模块外设，此外设可被配置为3个捕捉输入或者3个辅助脉宽调制器(APWM)输出；2个32位增强型正交脉冲(eQEP)外设；和2个外部存储器接口；1个用于速度较慢内存或者外设的异步和SDRAM外部存储器接口(EMIFA)，和1个用于SDRAM的较快速内存接口(EMIFB)。
以太网介质访问控制器(EMAC)在OMAP-L137和网络之间提供了1个高效端口。
EMAC支持10Base-T和100Base-TX，即半双工或全双工模式中的10M比特/秒(Mbps)和100Mbps。
此外，还为PHY配置提供了一个管理数据输入/输出(MDIO)接口。
HPI，I2C，SPI，USB1.1和USB2.0端口使得器件可以很容易地控制外设器件和/或者与主机处理器间的通信。
丰富的外设集提供了控制外围设备以及与外部处理器进行通信的能力。
如需了解每种外设的详细信息，请查阅本文件后面的有关章节以及相关联的外设参考指南。
此器件有一个用于包括此ARM和DSP的完整开发集。
这个开发集包括C编译器，1个用于简化编程和时序安排的DSP汇编优化器，和1个Windows®调试器接口，此接口用于源代码执行的可视性。
4 低功耗应用处理器 版权©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 1.4 功能方框图图1-1显示了器件的功能方框框图。
InputClock(s) SystemControl JTAGInterface PLL/ClockGenerator w/OSC GeneralPurpose Timer GeneralPurpose Timer(Watchdog) Power/SleepController RTC/ Pin 32-KHzOSC Multiplexing ARMSubsystem ARM926EJ-SCPUWithMMU 4KBETB 16KB16KBI-CacheD-Cache 8KBRAM(VectorTable) 64KBROM DSPSubsystem C674x™DSPCPU AET32KB32KBL1PgmL1RAM256KBL2RAM BOOTROM SwitchedCentralResource(SCR) PeripheralsDMA AudioPorts SerialInterfaces DisplayInternalMemory GPIO EDMA3 ControlTimers McASPw/FIFO
(3) I2C SPI UART
(2)
(2)
(3) Connectivity LCDCtlr 128KBRAM PRUSubsystem ExternalMemoryInterfaces eHRPWM
(3) eCAP
(3) eQEP
(2) USB2.0USB1.1(10/100) MMC/SDEMIFA(8b/16B) EMIFB OTGCtlrOHCICtlrEMACMDIO HPI (8b) NAND/FlashSDRAMOnly PHY PHY (RMII) 16bSDRAM (16b/32b) Note:Notallperipheralsareavailableatthesametimeduetomultiplexing. 图1-
1.OMAPL137功能方框图 版权©2012–2013,TexasInstrumentsIncorporated 低功耗应用处理器
5 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 1低功耗应用处理器........................................11.1特性..................................................11.2商标..................................................31.3说明..................................................41.4功能方框图...........................................5 2DeviceOverview........................................72.1DeviceCharacteristics...............................72.2DeviceCompatibility.................................82.3ARMSubsystem.....................................82.4DSPSubsystem....................................112.5MemoryMapSummary............................172.6BareDieInformation...............................212.7PinAssignments....................................282.8TerminalFunctions.................................29 3DeviceConfiguration.................................453.1Introduction.........................................453.2BootModesSupported.............................453.3SYSCFGModule...................................45 4DeviceOperatingConditions.......................48 4.1AbsoluteMaximumRatingsOverOperatingCaseTemperatureRange (UnlessOtherwiseNoted).................................484.2mendedOperatingConditions..............494.3ElectricalCharacteristics...........................50 5PeripheralInformationandElectrical Specifications..........................................515.1ParameterInformation..............................51 5.2mendedClockandControlSignalTransition Behavior............................................515.3PowerSupplies.....................................525.4Reset...............................................535.5CrystalOscillatororExternalClockInput..........555.6ClockPLLs.........................................565.7Interrupts............................................595.8General-PurposeInput/Output(GPIO).............675.9EDMA...............................................705.10ExternalMemoryInterfaceA(EMIFA).............755.11ExternalMemoryInterfaceB(EMIFB).............84 5.12MMC/SD/SDIO(MMCSD).......................905.13MediaessController(EMAC).........925.14ManagementDataInput/Output(MDIO)...........98 5.15MultichannelAudioSerialPorts(McASP0,McASP1, andMcASP2).....................................1005.16SerialPeripheralInterfacePorts(SPI0,SPI1)....1145.17EnhancedCaptureModule(eCAP)...............1325.18EnhancedQuadratureEncoderModule(eQEP)..135 5.19EnhancedHigh-ResolutionPulse-WidthModulator (eHRPWM)........................................1375.20LCDController....................................1405.21Timers.............................................1555.22Inter-IntegratedCircuitSerialPorts(I2C0,I2C1).157 5.23UniversalAsynchronousReceiver/Transmitter (UART)............................................1615.24USB1HostController(USB1.1OHCI)............1635.25USB0OTG(USB2.0OTG)........................1645.26UniversalHost-PortInterface(UHPI).............1725.27MemoryProtectionUnits(MPU)..................1765.28PowerandSleepController(PSC)................1785.29EmulationLogic...................................1815.30RealTimeClock(RTC)...........................1886DeviceandDocumentSupport...................1916.1DeviceSupport....................................1916.2DocumentationSupport...........................192 7MechanicalPackagingandOrderable Information............................................193 7.1DeviceandDevelopment-SupportTool Nomenclature.....................................1937.2PackagingMaterialsInformation..................1947.3ThermalDataforPTP.............................195 7.4SupplementaryInformationAboutthe176-pinPTP PowerPAD™Package............................1957.5PackagingInformation............................1967.6MechanicalDrawings.............................1967.7dMAX..............................................1987.8KeyManager......................................1987.9SECCTRL.........................................199RevisionHistory...........................................200
6 内容 SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 2DeviceOverview 2.1DeviceCharacteristics Table2-1providesanoverviewofOMAPL137.Thetableshowssignificantfeaturesofthedevice,includingthecapacityofon-chipRAM,peripherals,andthepackagetypewithpincount. Table2-
1.CharacteristicsoftheOMAPL137Processor HARDWAREFEATURESEMIFBEMIFAFlashCardInterfaceEDMA3dMAX Timers Peripherals Notallperipheralspinsareavailableatthesametime(formoredetail,seetheDeviceConfigurationssection). UART SPII2C MultichannelAudioSerialPort[McASP] 10/100MACwithManagementDataI/O eHRPWM eCAP eQEP UHPI USB2.0(USB0) USB1.1(USB1) General-PurposeInput/OutputPort LCDController RTC Size(Bytes) On-ChipMemory Organization C674xCPUID+CPURevID C674xMegamoduleRevision JTAGBSDL_ID ControlStatusRegister(CSR.[31:16]) RevisionIDRegister(MM_REVID[15:0]) DEVIDR0register CPUFrequency MHz SDRAMonly,16-bitbuswidth,upto256MbitAsynchronous(8-bitbuswidth)RAM,Flash,NOR,NAND MMCandSDcardssupported.32independentchannels,8QDMAchannels,2Transfercontrollers 16independentchannels264-BitGeneralPurpose(configurableas2separate32-bittimers,1configurableas WatchDog)3(onewithRTSandCTSflowcontrol)2(Eachwithonehardwarechipselect) 2(bothMaster/Slave) 3(eachwithtransmit/receive,FIFObuffer,16/12/4serializers) 1(RMIIInterface) 6SingleEdge,6DualEdgeSymmetric,or3DualEdgeAsymmetricOutputs332-bitcaptureinputsor332-bitauxiliaryPWMoutputs232-bitQEPchannelswith4inputs/channelFullSpeedHostOrDevicewithOn-ChipPHY- 8banksof16-bit 11(32KHzoscillatorandseperatepowertrail.Providestimeanddatetrackingandalarm capability.)488KBRAM,1088KBROM DSP32KBL1Program(L1P)/Cache(upto32KB) 32KBL1Data(L1D)/Cache(upto32KB)256KBUnifiedMappedRAM/Cache(L2) 1024KBROM(L2)DSPMemoriescanbemadeessibletoARM,EDMA3,andotherperipherals. ARM16KBI-Cache16KBD-Cache8KBRAM(VectorTable) 64KBROM ADDITIONALSHAREDMEMORY128KBRAM 0x1400 0x0000 0x8B7DF02F674xDSP300MHzARM926300MHz Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview
7 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 Table2-
1.CharacteristicsoftheOMAPL137Processor(continued) HARDWAREFEATURES CycleTime ns VoltagePackage ProductStatus
(1) Core(V)I/O(V) ProductPreview(PP),AdvanceInformation(AI),orProductionData(PD) 674xDSP3.33nsARM9263.33ns 1.2V3.3V24mmx24mm,176-Pin,0.5mmpitch,TQFP(PTP) AI
(1)ADVANCEINFORMATIONconcernsnewproductsinthesamplingorpreproductionphaseofdevelopment.Characteristicdataandotherspecificationsaresubjecttochangewithoutnotice.PRODUCTIONDATAinformationiscurrentasofpublicationdate.ProductsconformtospecificationsperthetermsoftheTexasInstrumentsstandardwarranty.Productionprocessingdoesnotnecessarilyincludetestingofallparameters. 2.2DeviceCompatibility TheARM926EJ-SRISCCPUpatiblewithotherARM9CPUsfromARMHoldingsplc. TheC674xDSPcoreispatiblewiththeC6000™DSPplatformandsupportsfeaturesofboththeC64x+andC67x+DSPfamilies. 2.3ARMSubsystem TheARMSubsystemincludesthefollowingfeatures:•ARM926EJ-SRISCprocessor•ARMv5TEJ(32/16-bit)instructionset•Littleendian•SystemControlCo-Processor15(CP15)•MMU•16KBInstructioncache•16KBDatacache•WriteBuffer•EmbeddedTraceModuleandEmbeddedTraceBuffer(ETM/ETB)•ARMInterruptcontroller 2.3.1ARM926EJ-SRISCCPU TheARMSubsystemintegratestheARM926EJ-Sprocessor.TheARM926EJ-SprocessorisamemberofARM9familyofgeneral-purposemicroprocessors.Thisprocessoristargetedatmulti-taskingapplicationswherefullmemorymanagement,highperformance,lowdiesize,andlowpowerareallimportant.TheARM926EJ-Sprocessorsupportsthe32-bitARMand16bitTHUMBinstructionsets,enablingtheusertotradeoffbetweenhighperformanceandhighcodedensity.Specifically,theARM926EJ-SprocessorsupportstheARMv5TEJinstructionset,whichincludesfeaturesforefficientexecutionofJavabytecodes,providingJavaperformancesimilartoJustinTime(JIT)Javainterpreter,butwithoutassociatedcodeoverhead. TheARM926EJ-SprocessorsupportstheARMdebugarchitectureandincludeslogictoassistinbothhardwareandsoftwaredebug.TheARM926EJ-SprocessorhasaHarvardarchitectureandprovidespletehighperformancesubsystem,including: •ARM926EJ-Sintegercore •CP15systemcontrolcoprocessor •MemoryManagementUnit(MMU)
8 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 •SeparateinstructionanddataCaches•Writebuffer•Separateinstructionanddata(internalRAM)interfaces•SeparateinstructionanddataAHBbusinterfaces•EmbeddedTraceModuleandEmbeddedTraceBuffer(ETM/ETB) ForpletedetailsontheARM9,refertotheARM926EJ-STechnicalReferenceManual,availableat 2.3.2CP15 TheARM926EJ-Ssystemcontrolcoprocessor(CP15)isusedtoconfigureandcontrolinstructionanddatacaches,MemoryManagementUnit(MMU),andotherARMsubsystemfunctions.TheCP15registersareprogrammedusingtheMRCandMCRARMinstructions,whentheARMinaprivilegedmodesuchassupervisororsystemmode. 2.3.3MMU Asinglesetoftwolevelpagetablesstoredinmainmemoryisusedtocontroltheaddresstranslation,permissionchecksandmemoryregionattributesforbothdataandinstructionesses.TheMMUusesasingleunifiedTranslationLookasideBuffer(TLB)tocachetheinformationheldinthepagetables.TheMMUfeaturesare:•StandardARMarchitecturev4andv5MMUmappingsizes,domainsandessprotectionscheme.•Mappingsizesare: –1MB(sections)–64KB(largepages)–4KB(smallpages)–1KB(tinypages)•esspermissionsforlargepagesandsmallpagescanbespecifiedseparatelyforeachquarterofthepage(subpagepermissions)•Hardwarepagetablewalks•InvalidateentireTLB,usingCP15register8•InvalidateTLBentry,selectedbyMVA,usingCP15register8•LockdownofTLBentries,usingCP15register10 2.3.4CachesandWriteBuffer ThesizeoftheInstructionCacheis16KB,Datacacheis16KB.Additionally,theCacheshavethefollowingfeatures: •Virtualindex,virtualtag,andaddressedusingtheModifiedVirtualAddress(MVA) •Four-waysetassociative,withacachelinelengthofeightwordsperline(32-bytesperline)andwithtwodirtybitsintheDcache •Dcachesupportswrite-throughandwrite-back(orcopyback)cacheoperation,selectedbymemoryregionusingtheCandBbitsintheMMUtranslationtables. •Critical-wordfirstcacherefilling •Cachelockdownregistersenablecontroloverwhichcachewaysareusedforallocationonalinefill,providingamechanismforbothlockdown,andcontrollingcachecorruption •DcachestoresthePhysicalAddressTAG(PATAG)correspondingtoeachDcacheentryintheTAGRAMforuseduringthecachelinewrite-backs,inadditiontotheVirtualAddressTAGstoredintheTAGRAM.ThismeansthattheMMUisnotinvolvedinDcachewrite-backoperations,removingthepossibilityofTLBmissesrelatedtothewrite-backaddress. •Cachemaintenanceoperationsprovideefficientinvalidationof,theentireDcacheorIcache,regionsoftheDcacheorIcache,andregionsofvirtualmemory. Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview
9 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 Thewritebufferisusedforallwritestoanoncachablebufferableregion,write-throughregionandwritemissestoawrite-backregion.AseparatebufferisincorporatedintheDcacheforholdingwrite-backforcachelineevictionsorcleaningofdirtycachelines.Themainwritebufferhas16-worddatabufferandafour-addressbuffer.TheDcachewrite-backhaseightdatawordentriesandasingleaddressentry. 2.3.5AdvancedHigh-PerformanceBus(AHB) TheARMSubsystemusestheAHBportoftheARM926EJ-StoconnecttheARMtotheConfigbusandtheexternalmemories.ArbitersareemployedtoarbitrateesstotheseparateD-AHBandI-AHBbytheConfigBusandtheexternalmemoriesbus. 2.3.6EmbeddedTraceMacrocell(ETM)andEmbeddedTraceBuffer(ETB) Tosupportreal-timetrace,theARM926EJ-SprocessorprovidesaninterfacetoenableconnectionofanEmbeddedTraceMacrocell(ETM).TheARM926EJ-SSubsysteminthedevicealsoincludestheEmbeddedTraceBuffer(ETB).TheETMconsistsoftwoparts:•TracePortprovidesreal-timetracecapabilityfortheARM9.•Triggeringfacilitiesprovidetriggerresources,whichincludeaddressandparators,counter, andsequencers. ThedevicetraceportisnotpinnedoutandisinsteadonlyconnectedtotheEmbeddedTraceBuffer.TheETBhasa4KBbuffermemory.ETBenableddebugtoolsarerequiredtoread/interpretthecapturedtracedata. ThisdeviceusesETM9™versionr2p2andETBversionr0p1.DocumentationontheETMandETBisavailablefromARMLtd.Referencethe'CoreSight™ETM9™TechnicalReferenceManual,revisionr0p1'andthe'ETM9TechnicalReferenceManual,revisionr2p2'. 2.3.7ARMMemoryMapping BydefaulttheARMhasesstomostonandoffchipmemoryareas,includingtheDSPInternalmemories,EMIFA,EMIFB,andtheadditional128KbyteonchipsharedSRAM.LikewisealmostalloftheonchipperipheralsareessibletotheARMbydefault. Toimprovesecurityand/orrobustnessthedevicehasextensivememoryandperipheralprotectionunitswhichcanbeconfiguredtolimitessrightstothevariouson/offchipresourcestospecifichosts;includingtheARMaswellasothermasterperipherals.ThisallowsthesystemtaskstobepartitionedbetweentheARMandDSPasbestsuitestheparticularapplication;whileenhancingtheoverallrobustnessofthesolution. SeeTable2-3foralevelOMAPL137memorymapthatincludestheARMmemoryspace. 10 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated 2.4DSPSubsystem TheDSPSubsystemincludesthefollowingfeatures:•C674xDSPCPU•32KBL1Program(L1P)/Cache(upto32KB)•32KBL1Data(L1D)/Cache(upto32KB)•256KBUnifiedMappedRAM/Cache(L2)•1MBMask-programmableROM•Littleendian OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 32KBytesL1PRAM/ Cache 256 256KBytesL2RAM 256 BootROM256 256CacheControlMemoryProtectL1PBandwidthMgmt CacheControlMemoryProtectL2BandwidthMgmt 256 256 InstructionFetch C674xFixed/FloatingPointCPU RegisterFileA 64 RegisterFileB 64 256 IDMA256 256 PowerDown InterruptController BandwidthMgmtMemoryProtectL1DCacheControl EMC CFG MDMA SDMA 8x32 64 6464 64 32KBytesL1DRAM/ Cache HighPerformanceSwitchFabric 32ConfigurationPeripheralsBus Figure2-
1.C674xMegamoduleBlockDiagram Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview 11 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 2.4.1C674xDSPCPUDescription TheC674xCentralProcessingUnit(CPU)consistsofeightfunctionalunits,tworegisterfiles,andtwodatapathsasshowninFigure2-
2.Thetwogeneral-purposeregisterfiles(AandB)eachcontain3232bitregistersforatotalof64registers.Thegeneral-purposeregisterscanbeusedfordataorcanbedataaddresspointers.Thedatatypessupportedincludepacked8-bitdata,packed16-bitdata,32-bitdata,40bitdata,and64-bitdata.Valueslargerthan32bits,suchas40-bit-longor64-bit-longvaluesarestoredinregisterpairs,withthe32LSBsofdataplacedinanevenregisterandtheremaining8or32MSBsinthenextupperregister(whichisalwaysanodd-numberedregister). Theeightfunctionalunits(.M1,.L1,.D1,.S1,.M2,.L2,.D2,and.S2)areeachcapableofexecutingoneinstructioneveryclockcycle.The.Mfunctionalunitsperformallmultiplyoperations.The.Sand.Lunitsperformageneralsetofarithmetic,logical,andbranchfunctions.The.Dunitsprimarilyloaddatafrommemorytotheregisterfileandstoreresultsfromtheregisterfileintomemory. TheC674xbinestheperformanceoftheC64x+corewiththefloating-pointcapabilitiesoftheC67xcore. EachC674x.Munitcanperformoneofthefollowingeachclockcycle:one32x32bitmultiply,one16x32bitmultiply,two16x16bitmultiplies,two16x32bitmultiplies,two16x16bitmultiplieswithadd/subtractcapabilities,four8x8bitmultiplies,four8x8bitmultiplieswithaddoperations,andfour16x16multiplieswithadd/subtractcapabilities(includingplexmultiply).ThereisalsosupportforGaloisfieldmultiplicationfor8-bitand32-bitdata.municationsalgorithmssuchasFFTsandmodemsplexmultiplication.plexmultiply(CMPY)instructiontakesfour16-bitinputsandproducesa32-bitrealanda32-bitimaginaryoutput.Thereareplexmultiplieswithroundingcapabilitythatproducesone32-bitpackedoutputthatcontain16-bitrealand16-bitimaginaryvalues.The32x32bitmultiplyinstructionsprovidetheextendedprecisionnecessaryforaudioandotherhighprecisionalgorithmsonavarietyofsignedandunsigned32-bitdatatypes. The.Lor(ArithmeticLogicUnit)nowincorporatestheabilitytodoparalleladd/subtractoperationsonapairmoninputs.Versionsofthisinstructionexisttoworkon32-bitdataoronpairsof16-bitdataperformingdual16-bitaddandsubtractsinparallel.Therearealsosaturatedformsoftheseinstructions. TheC674xcoreenhancesthe.Sunitinseveralways.Onpreviouscores,dual16-bitMIN2andparisonswereonlyavailableonthe.Lunits.OntheC674xcoretheyarealsoavailableonthe.Sunitwhichincreasestheperformanceofalgorithmsthatdosearchingandsorting.Finally,toincreasedatapackingandunpackingthroughput,the.Sunitallowssustainedhighperformanceforthequad8-bit/16-bitanddual16-bitinstructions.Unpackinstructionsprepare8-bitdataforparallel16-bitoperations.Packinstructionsreturnparallelresultstooutputprecisionincludingsaturationsupport. Othernewfeaturesinclude: •SPLOOP-AsmallinstructionbufferintheCPUthataidsincreationofsoftwarepipeliningloopswheremultipleiterationsofaloopareexecutedinparallel.TheSPLOOPbufferreducesthecodesizeassociatedwithsoftwarepipelining.Furthermore,loopsintheSPLOOPbufferarefullyinterruptible. •CompactInstructions-ThenativeinstructionsizefortheC6000devicesis32bits.moninstructionssuchasMPY,AND,OR,ADD,andSUBcanbeexpressedas16bitsifthepilercanrestrictthecodetousecertainregistersintheregisterfile.pressionisperformedbythecodegenerationtools. •InstructionSetEnhancement-Asnotedabove,therearenewinstructionssuchas32-bitmultiplications,plexmultiplications,packing,sorting,bitmanipulation,and32-bitGaloisfieldmultiplication. •ExceptionsHandling-Intendedtoaidtheprogrammerinisolatingbugs.TheC674xCPUisabletodetectandrespondtoexceptions,bothfrominternallydetectedsources(suchasillegalop-codes)andfromsystemevents(suchasawatchdogtimeexpiration). •Privilege-Definesuserandsupervisormodesofoperation,allowingtheoperatingsystemtogiveabasiclevelofprotectiontosensitiveresources.Localmemoryisdividedintomultiplepages,eachwithread,write,andexecutepermissions. 12 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 •Time-StampCounter-PrimarilytargetedforReal-TimeOperatingSystem(RTOS)robustness,afreerunningtime-stampcounterisimplementedintheCPUwhichisnotsensitivetosystemstalls. FormoredetailsontheC674xCPUanditsenhancementsovertheC64xarchitecture,seethefollowingdocuments:•TMS320C64x/C64x+DSPCPUandInstructionSetReferenceGuide(literaturenumberSPRU732)•TMS320C64xTechnicalOverview(literaturenumberSPRU395) Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview 13 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 DatapathA ST1bST1a 32MSB32LSB LD1bLD1a 32MSB32LSB DA1 DA2 LD2aLD2b 32LSB32MSB DatapathB ST2aST2b 32MSB32LSB src1 .L1src2 odddst evendst longsrc
8 longsrcevendstodddst.S1src1 src2 dst2dst1.M1src1src2 8 3232 dst.D1src1 src2 src2.D2src1 dst src2 .M2src1 dst2 32 dst1 32 src2 src1 .S2odddst evendst longsrc
8 Oddregister fileA(A1,A3,A5...A31) (D) Evenregister fileA(A0,A2,A4...A30) (D) (A)(B)(C) 2x 1xOdd registerfileB (B1,B3,B5...B31) Evenregister fileB(B0,B2,B4...B30) (C) (B)(A) (D) 8longsrcevendst (D) odddst.L2 src2 src1 ControlRegister Figure2-
2.TMS320C674x™CPU(DSPCore)DataPaths 2.4.2DSPMemoryMappingTheDSPmemorymapisshowninSection2.5 14 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 BydefaulttheDSPalsohasesstomostonandoffchipmemoryareas,withtheexceptionoftheARMRAM,ROM,andAINTCinterruptcontroller.TheDSPalsobootsfirst,andmustreleasetheARMfromresetbeforetheARMcanexecuteanycode. Additionally,theDSPmegamoduleincludesthecapabilitytolimitesstoitsinternalmemoriesthroughitsSDMAport;withoutneedinganexternalMPUunit. 2.4.2.1ARMInternalMemoriesTheDSPdoesnothaveesstotheARMinternalmemory. 2.4.2.2ExternalMemories TheDSPhasesstothefollowingExternalmemories:•AsynchronousEMIF/SDRAM/NAND/NORFlash(EMIFA)•SDRAM(EMIFB) 2.4.2.3DSPInternalMemories TheDSPhasesstothefollowingDSPmemories:•L2RAM•L1PRAM•L1DRAM 2.4.2.4C674xCPU TheC674xcoreusesatwo-levelcache-basedarchitecture.TheLevel1Programcache(L1P)is32KBdirectmappedcacheandtheLevel1Datacache(L1D)is32KB2-waysetassociatedcache.TheLevel2memory/cache(L2)consistsofa256KBmemoryspacethatissharedbetweenprogramanddataspace.L2memorycanbeconfiguredasmappedmemory,cache,orbinationofboth. Table2-2showsamemorymapoftheC674xCPUcacheregistersforthedevice. HEXADDRESSRANGE0x018400000x018400200x018400240x018400400x01840044 0x01840048-0x01840FFC0x01841000 0x01841004-0x01841FFC0x018420000x018420040x018420080x0184200C 0x01842010-0x01843FFF0x018440000x018440040x018440100x018440140x018440180x0184401C0x01844020 Table2-
2.C674xCacheRegisters REGISTERACRONYML2CFGL1PCFGL1PCCL1DCFGL1DCC- EDMAWEIGHT- L2ALLOC0L2ALLOC1L2ALLOC2L2ALLOC3 L2WBARL2WWCL2WIBARL2WIWCL2IBAR L2IWCL1PIBAR DESCRIPTIONL2CacheconfigurationregisterL1PSizeCacheconfigurationregisterL1PFreezeModeCacheconfigurationregisterL1DSizeCacheconfigurationregisterL1DFreezeModeCacheconfigurationregisterReservedL2EDMAesscontrolregisterReservedL2allocationregister0L2allocationregister1L2allocationregister2L2allocationregister3ReservedL2writebackbaseaddressregisterL2writebackwordcountregisterL2writebackinvalidatebaseaddressregisterL2writebackinvalidatewordcountregisterL2invalidatebaseaddressregisterL2invalidatewordcountregisterL1Pinvalidatebaseaddressregister Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview 15 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 HEXADDRESSRANGE0x018440240x018440300x018440340x018440380x018440400x018440440x018440480x0184404C 0x01844050-0x01844FFF0x018450000x018450040x01845008 0x0184500C-0x018450270x01845028 0x0184502C-0x018450390x018450400x018450440x01845048 0x01848000–0x018480FF 0x01848100–0x0184817F 0x01848180–0x01848187 0x01848188–0x0184818F 0x01848190–0x01848197 0x01848198–0x0184819F 0x018481A0–0x018481FF 0x01848200 0x01848204–0x018482FF 0x01848300–0x0184837F 0x01848380–0x018483FF Table2-
2.C674xCacheRegisters(continued) REGISTERACRONYML1PIWC L1DWIBARL1DWIWC L1DWBARL1DWWCL1DIBAR L1DIWC- L2WBL2WBINV L2INV- L1PINV- L1DWBL1DWBINV L1DINVMAR0-MAR63 MAR64–MAR95 MAR96-MAR97 MAR98–MAR99 MAR100–MAR101 MAR102–MAR103 MAR104–MAR127 MAR128 MAR129–MAR191 MAR192–MAR223 MAR224–MAR255 DESCRIPTIONL1PinvalidatewordcountregisterL1DwritebackinvalidatebaseaddressregisterL1DwritebackinvalidatewordcountregisterReservedL1DBlockWritebackL1DBlockWritebackL1DinvalidatebaseaddressregisterL1DinvalidatewordcountregisterReservedL2writebackallregisterL2writebackinvalidateallregisterL2GlobalInvalidatewithoutwritebackReservedL1PGlobalInvalidateReservedL1DGlobalWritebackL1DGlobalWritebackwithInvalidateL1DGlobalInvalidatewithoutwritebackReserved0x00000000–0x3FFFFFFFMemoryAttributeRegistersforEMIFASDRAMData(CS0)0x40000000–0x5FFFFFFFMemoryAttributeRegistersforEMIFAAsyncData(CS2)0x60000000–0x61FFFFFFMemoryAttributeRegistersforEMIFAAsyncData(CS2)0x62000000–0x63FFFFFFMemoryAttributeRegistersforEMIFAAsyncData(CS2)0x64000000–0x65FFFFFFMemoryAttributeRegistersforEMIFAAsyncData(CS2)0x66000000–0x67FFFFFFReserved0x68000000–0x7FFFFFFFMemoryAttributeRegisterforSharedRAM0x80000000–0x8001FFFFReserved0x80020000–0x81FFFFFFReserved0x82000000–0xBFFFFFFFMemoryAttributeRegistersforEMIFDSDRAMData(CS2)0xC0000000–0xDFFFFFFFReserved0xE0000000–0xFFFFFFFF SeeTable2-3foralevelOMAPL137memorymapthatincludestheDSPmemoryspace. 16 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 2.5MemoryMapSummary StartAddress 0x00000000 0x00001000 0x007000000x008000000x00840000 0x00E000000x00E080000x00F000000x00F08000 0x01800000 0x01810000 0x018110000x018120000x018130000x018200000x01830000 0x01840000 0x018500000x01880000 0x01BC04000x01BC04300x01BC0000 0x01BC10000x01BC1800 0x01BC0500 0x01BD00000x01BE00000x01C000000x01C080000x01C084000x01C088000x01C100000x01C110000x01C120000x01C14000 EndAddress 0x00000FFF 0x006FFFFF 0x007FFFFF0x0083FFFF0x00DFFFFF 0x00E07FFF0x00EFFFFF0x00F07FFF0x017FFFFF 0x0180FFFF 0x01810FFF 0x01811FFF0x01812FFF0x0181FFFF0x0182FFFF0x0183FFFF 0x0184FFFF 0x0187FFFF0x01BC03FF 0x01BC042F0x01BC044F0x01BC0FFF 0x01BC17FF0x01BC18FF 0x01BCFFFF 0x01BDFFFF0x01BFFFFF0x01C07FFF0x01C083FF0x01C087FF0x01C0FFFF0x01C10FFF0x01C11FFF0x01C13FFF0x01C14FFF Table2-
3.OMAPL137TopLevelMemoryMap Size ARMMemDSPMemMapEDMAMemdMAXMem Map Map Map 4K - 6M+1020K1024K256K5M+768K 32K992K32K8M+992K64K 4K 4K4K52K64K64K 64K 192K3M+257K 48324K 2K256 62K+76864K128K32K1024102430K4K4K8K4K - - - - ARMETBmemoryARMETBregARMIceCrusher - DSPL2ROMDSPL2RAM - DSPL1PRAM- DSPL1DRAM- DSPInterruptController DSPPowerdownController DSPSecurityIDDSPRevisionID DSPEMCDSPInternalReservedDSPMemory System- - - EDMA3CCEDMA3TC0EDMA3TC1PSC0PLLControllerSYSCFG dMAXLocalAddressSpace - - - - MasterPeripheralMemMap - LCDCMemMap - Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview 17 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 StartAddress 0x01C150000x01C160000x01C170000x01C180000x01C200000x01C210000x01C220000x01C230000x01C240000x01C250000x01C300000x01C30200 0x01C320000x01C32200 0x01C340000x01C380000x01C390000x01C3C0000x01C3D0000x01C400000x01C410000x01C420000x01C430000x01C440000x01D000000x01D010000x01D020000x01D030000x01D040000x01D050000x01D060000x01D070000x01D080000x01D090000x01D0A0000x01D0B0000x01D0C0000x01D0D0000x01D0E0000x01D0F0000x01E000000x01E100000x01E110000x01E12000 Table2-
3.OMAPL137TopLevelMemoryMap(continued) EndAddressSize ARMMemMap DSPMemMap EDMAMemMap dMAXMemMap 0x01C15FFF0x01C16FFF0x01C17FFF0x01C1FFFF0x01C20FFF0x01C21FFF0x01C22FFF0x01C23FFF0x01C24FFF0x01C2FFFF0x01C301FF0x01C31FFF 0x01C321FF0x01C33FFF 0x01C37FFF0x01C38FFF0x01C3BFFF0x01C3CFFF0x01C3FFFF0x01C40FFF0x01C41FFF0x01C42FFF0x01C43FFF0x01CFFFFF0x01D00FFF0x01D01FFF0x01D02FFF0x01D03FFF0x01D04FFF0x01D05FFF0x01D06FFF0x01D07FFF0x01D08FFF0x01D09FFF0x01D0AFFF0x01D0BFFF0x01D0CFFF0x01D0DFFF0x01D0EFFF0x01DFFFFF0x01E0FFFF0x01E10FFF0x01E11FFF0x01E12FFF 4K4K4K32K4K4K4K4K4K44K5127K+5125127K+51216K4K12K4K12K4K4K4K4K752K4K4K4K4K4K4K4K4K4K4K4K4K4K4K4K964K64K4K4K4K Timer64P0Timer64P1I2C0RTCdMAXDataRAM0- dMAXDataRAM1- dMAXControlRegistersdMAXMAX0ConfigurationMemory dMAXMAX1ConfigurationMemory MMC/SD0 SPI0UART0 McASP0ControlMcASP0AFIFOCtrlMcASP0DataMcASP1ControlMcASP1AFIFOCtrlMcASP1DataMcASP2ControlMcASP2AFIFOCtrlMcASP2DataUART1UART2USB0UHPISPI1 MasterPeripheralMemMap LCDCMemMap - - - - - - - - - - - - 18 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 StartAddress 0x01E130000x01E140000x01E150000x01E160000x01E200000x01E220000x01E230000x01E240000x01E250000x01E260000x01E270000x01E280000x01E290000x01E2A0000x01F000000x01F010000x01F020000x01F030000x01F040000x01F050000x01F060000x01F070000x01F080000x01F090000x01F0A0000x01F0B0000x01F0C000 0x117000000x118000000x11840000 0x11E000000x11E080000x11F000000x11F08000 0x400000000x600000000x620000000x640000000x660000000x680000000x68008000 0x80000000 Table2-
3.OMAPL137TopLevelMemoryMap(continued) EndAddressSize ARMMemMap DSPMemMap EDMAMemMap dMAXMemMap 0x01E13FFF0x01E14FFF0x01E15FFF0x01E1FFFF0x01E21FFF0x01E22FFF0x01E23FFF0x01E24FFF0x01E25FFF0x01E26FFF0x01E27FFF0x01E28FFF0x01E29FFF0x01EFFFFF0x01F00FFF0x01F01FFF0x01F02FFF0x01F03FFF0x01F04FFF0x01F05FFF0x01F06FFF0x01F07FFF0x01F08FFF0x01F09FFF0x01F0AFFF0x01F0BFFF0x116FFFFF 0x117FFFFF0x1183FFFF0x11DFFFFF 0x11E07FFF0x11EFFFFF0x11F07FFF0x3FFFFFFF 0x5FFFFFFF0x61FFFFFF0x63FFFFFF0x65FFFFFF0x67FFFFFF0x68007FFF0x7FFFFFFF 0x8001FFFF 4K4K4K40K8K4K4K4K4K4K4K4K4K856K4K4K4K4K4K4K4K4K4K4K4K4K247M+976K1024K256K5M+768K32K992K32K736M+992K512M32M32M32M32M32K383M+992K128K LCDControllerMPU1MPU2- EMACControlModuleRAMEMACControlModuleRegisters EMACControlRegistersEMACMDIOportUSB1GPIOPSC1I2C1EPWM0HRPWM0eHRPWM1HRPWM1eHRPWM2HRPWM2ECAP0ECAP1ECAP2EQEP0EQEP1- DSPL2ROMDSPL2RAM - DSPL1PRAM- DSPL1DRAM- EMIFASDRAMdata(CS0)EMIFAasyncdata(CS2)EMIFAasyncdata(CS3)EMIFAasyncdata(CS4)EMIFAasyncdata(CS5) EMIFAControlRegs- SharedRAM MasterPeripheralMemMap LCDCMemMap - - - - - - - - Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview 19 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 StartAddress 0x800200000xB00000000xB00080000xC00000000xE00000000xFFFD00000xFFFE00000xFFFEE0000xFFFF00000xFFFF2000 Table2-
3.OMAPL137TopLevelMemoryMap(continued) EndAddressSize ARMMemMap DSPMemMap EDMAMemMap dMAXMemMap 0xAFFFFFFF 0xB0007FFF0xBFFFFFFF 0xDFFFFFFF0xFFFCFFFF 0xFFFDFFFF 0xFFFEDFFF0xFFFEFFFF 0xFFFF1FFF 0xFFFFFFFF 767M+896K32K 255M+992K512M 511M+832K64K 56K8K 8K 56K ARMlocalROM ARMInterruptControllerARMlocalRAM - EMIFBControlRegs- EMIFBSDRAMData- - - - - MasterPeripheralMemMap TheDSPL2ROMisusedforbootpurposesandcannotbeprogrammedwithapplicationcode. LCDCMemMap 20 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated 2.6BareDieInformation DIETHICKNESS BACKSIDEFINISH 380µm Siliconwithbackgrind OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 BACKSIDEPOTENTIAL Floating BONDPADMETALLIZATIONCOMPOSITION TaN/AlCu BONDPADTHICKNESS 1000nm Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview 21 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 DESCRIPTIONAXR1_00UART0_RXDUART0_TXDAXR1_10VDDSHVN/CVSSAXR1_11SPI0_SCSNVDDSPI0_CLKSPI0_ENANSPI1_SOMISPI1_SIMOVDDSHVVSSN/CSPI1_CLKSPI0_SOMISPI0_SIMOEMA_WAITVDDEMA_OENEMA_CSN_2VDDSHVN/CVSSN/CN/CEMA_BA_1EMA_A_10VDDEMA_A_00EMA_A_01EMA_A_02EMA_A_03VDDSHVVSSN/CEMA_A_04EMA_A_05EMA_A_06EMA_A_07VDDEMA_A_08EMA_A_09EMA_A_11 Table2-
4.BondPadCoordinatesinMicrons PADNUMBER1234567891011121314151617181920212223242526272829303132333435363738394041424344454647 XMIN209.005279.005349.005419.005509.005582.755652.755722.755792.755862.755932.7551002.7551072.7551142.7551212.7551299.0051372.7551442.7551512.7551582.7551652.7551722.7551792.7551862.7551932.7552002.7552089.0052159.0052229.0052299.0052369.0052439.0052509.0052579.0052649.0052719.0052789.0052879.0052954.0053024.0053094.0053164.0053234.0053304.0053374.0053444.0053514.005 YMIN13.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.22513.225 XMAX274.005344.005414.005484.005574.005647.755717.755787.755857.755927.755997.7551067.7551137.7551207.7551277.7551364.0051437.7551507.7551577.7551647.7551717.7551787.7551857.7551927.7551997.7552067.7552154.0052224.0052294.0052364.0052434.0052504.0052574.0052644.0052714.0052784.0052854.0052944.0053019.0053089.0053159.0053229.0053299.0053369.0053439.0053509.0053579.005 YMAX78.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.22578.225 22 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT DESCRIPTIONEMA_A_12N/CVDDSHVN/CN/CN/CN/CVSSN/CEMA_D_00N/CEMA_D_01EMA_D_02N/CN/CVDDSHVN/CVSSEMA_D_03N/CEMA_D_04N/CVDDN/CEMA_D_05N/CEMA_D_06N/CVSSVDDSHVN/CN/CN/CEMA_D_07N/CEMA_WENN/CVDDVSSN/CVDDSHVVDDSHVVDDVDDN/CVSSN/C ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 Table2-
4.BondPadCoordinatesinMicrons(continued) PADNUMBER4849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394 XMIN3584.0053654.0053739.0053814.0053884.0053954.0054024.0054094.0054284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.785 YMIN13.22513.22513.22513.22513.22513.22513.22513.225209.005279.435349.865420.295510.725580.91650.91720.91790.91860.91930.911000.911070.911140.911210.911280.911355.8851444.971514.971584.971654.971724.971794.971864.971934.972004.972074.972150.6152235.3452305.3452375.3452445.3452515.3452585.3452655.3452725.3452795.3452865.3452935.345 XMAX3649.0053719.0053804.0053879.0053949.0054019.0054089.0054159.0054349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.785 YMAX78.22578.22578.22578.22578.22578.22578.22578.225274.005344.435414.865485.295575.725645.91715.91785.91855.91925.91995.911065.911135.911205.911275.911345.911420.8851509.971579.971649.971719.971789.971859.971929.971999.972069.972139.972215.6152300.3452370.3452440.3452510.3452580.3452650.3452720.3452790.3452860.3452930.3453000.345 Copyright©2012–2013,TexasInstrumentsIncorporated SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT DeviceOverview 23 OMAPL137-HT ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 DESCRIPTIONVDDSHVVDDAR1N/CN/CVDDNWA1VDDNWA1VDDVSSVDDSHVN/CN/CVSSN/CVDDSHVVDDN/CN/CVSSN/CVDDSHVVSSN/CN/CVDDSHVVSSVDDSHVVDDN/CVSSVDDSHVVDDVSSVDDSHVAXR0_00N/CAXR0_01AXR0_02VDDN/CN/CN/CN/CN/CAXR0_03N/CAXR0_05AXR0_06 Table2-
4.BondPadCoordinatesinMicrons(continued) PADNUMBER9596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141 XMIN4284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854284.7854090.7654020.5553949.2153878.8853808.4153738.313663.7353588.513518.4153447.745 YMIN3015.7753106.2053176.6353247.0653325.9253400.023470.023540.023610.023680.023750.023824.2253913.463983.464053.464123.464193.464263.464333.464407.6654497.344567.344637.344707.344777.344847.344917.344987.345061.5355150.3455220.3455290.3455360.3455430.3455500.3455574.5455665.4455861.2255861.2255861.2255861.2255861.2255861.2255861.2255861.2255861.2255861.225 XMAX4349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854349.7854155.7654085.5554014.2153943.8853873.4153803.313728.7353653.513583.4153512.745 YMAX3080.7753171.2053241.6353312.0653390.9253465.023535.023605.023675.023745.023815.023889.2253978.464048.464118.464188.464258.464328.464398.464472.6654562.344632.344702.344772.344842.344912.344982.345052.345126.5355215.3455285.3455355.3455425.3455495.3455565.3455639.5455730.4455926.2255926.2255926.2255926.2255926.2255926.2255926.2255926.2255926.2255926.225 24 DeviceOverview SubmitDocumentationFeedbackProductFolderLinks:OMAPL137-HT Copyright©2012–2013,TexasInstrumentsIncorporated OMAPL137-HT DESCRIPTIONVSSVDDSHVAXR0_07AXR0_08AFSX0VDDSHVN/CVSSAHCLKR0AFSR0VPPVPPIFORCEVSENSEVDDA18V_USB1VSSUSB1_DPN/CUSB1_DMVDDA33_USB1VDDVSSUSB0_IDUSB0_VBUSVDDA12_USB0VDDA18_USB0VSSA_USB0USB0_DPN/CUSB0_DMVSSA33_USB0VDDA33_USB0VSSVDDA12_PLLVSSA12_PLLOSCINOSCVSSRESETNVDDN/CRTC_XIRTC_VSSRTC_XOVDD2N/CTRSTNTRSTN ZHCS706B–FEBRUARY2012–REVISEDFEBRUARY2013 Table2-
4.BondPadCoordinatesinMicrons(continued) PADNUMBER142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188 XMIN3376.0353304.273233.6453163.253089.8753019.1152948.6252869.3952798.8352726.122652.812581.052510.132439.422369.1552298.6852228.452158.2752087.535200
声明：
该资讯来自于互联网网友发布，如有侵犯您的权益请联系我们。