1 —–VerilogHDL VerilogHDL VerilogHDL TLB/Cache FPU CPU / UARTPS/2 VGA I2C PCI CPUI/O VerilogHDL 1.1 PC 16GBCPU 3GHz
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1 ( ) ( ) ) ( I/O ( “”)) CD/DVD I/O(USBMemory) 1.1ALUFPUCacheTLB VerilogHDL CPU( ) I/O ALUFPUCacheTLB I/OI/O CPU I/OCD/DVD 1.1.2 I/O( 1.1) Hardware/SoftwareCo-Design (Hardware) 2040 40 ENIAC ( ) 1.12050 20 60 (IntegratedCircuit) (Fairchild) 6600IBM360( Architecture) IBM7000 CDC6000 (TexasInstruments)370)IBM360(ComputerOrganization) 75 5.1MHz 256KB∼1MB PC(PersonalComputers) 20 60
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1 CPU CPU CPU ( (Immediate) CPUCPU ) 825632 (Instruc) 832(CPU
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(7) x86MIPS 16
(2)(5) 32 unsignedintmul16(unsignedintx,unsignedinty){ unsignedinta,b,c; unsignedinti;//counter a=x;//multiplicand b=y;//multiplier c=0;//product for(i=0;i<16;i++){//for16bits if((b&1)==1){//LSBofbis1 c+=a;//c=c+a } a=a<<1;//shifta1-bitleft b=b>>1;//shiftb1-bitright } return(c); //returnproduct } −O4−
S c=a*b(GNUC CPU4) x86x86 mul16: pushlmovlmovl %ebp%esp,%ebp8(%ebp),%ecx
(6)I/OC 1.1
5 .L6:.L5: pushl%ebxmovl12(%ebp),%edxxorl%ebx,%ebxmovl$15,%eax.p2align2,,
3 testbjeaddl $
1,%dl.L5%ecx,%ebx sallshrldecljnsmovlpoplleaveret %ecx%edx%eax.L6%ebx,%ebx %eax C32 32 c+=a%ebx
C addl%ecx,%ebx addl %ecx%ebx %ecx%ebx %ebx x86 −O4−
S MIPS mul16:$L6:$L5: .frame.mask.fmask.set.setmoveli andiaddiubeqsrladdu bgezslljmove $sp,
0,$31#vars=0,regs=0/0,args=0,gp=
0 0x00000000,
0 0x00000000,
0 noreorder nomacro $
6,$0 $3,15 #0xf $
2,$5,0x1$
3,$3,-1$
2,$0,$L5$
5,$5,1$
6,$6,$
4 $
3,$L6$
4,$4,1$31$
2,$6
6 Caddurd,rs,rt MIPS c+=ard srlsllmove(DelayedBranch)
1 addu$
6,$6,$4rsrt RISC CPUbeqbgezj 0xCPU (umulator) 6502Z80CPUCPU (Stack) Machine)1.1add Bytecode 1.1 Java JVM(JavaVirtual xyz addx,y,z addx,y addx add x8632 8( ) eaxebxecxedxebpespesiedi 3(log28=323=8) x86 x86 ( )
8 CPU CPU mul16:.L6: pushl%ebp ;01010101 movl%esp,%ebp ;
1 movl8(%ebp),%ecx;100001000 pushl%ebx ;01010011 movl12(%ebp),%edx;100001100 xorl%ebx,%ebx ;
1 movl$15,%eax ;10111000 .p2align2,,
3 ;00 ;000000000 1.1
7 .L5: 32$L6:$L5: testbjeaddl $
1,%dl.L5%ecx,%ebx ;000000001;0;
1 sallshrldecljnsmovlpoplleaveret %ecx%edx%eax.L6%ebx,%ebx %eax MIPS5 MIPS MIPS MIPSCPU moveli $
6,$0$3,15 ;1;0;01001000;0;0;01011011;11001001;11000011 MIPS MIPS32 CPUx86CPU #01#11 andiaddiubeqsrladdu $
2,$5,0x1#01$
3,$3,-1#11$
2,$0,$L5#10$
5,$5,1#10$
6,$6,$4#01 bgezslljmove MIPS $
3,$L6$
4,$4,1$31$
2,$6 x86MIPS #10#00#00#01 RISC x86 CISC MIPS 1.1.4CISCRISC CISC(ComplexInstructionSetComputer) CPU MC68000PDP-11CISC VAX CISC1980 Intelx86(IA-32IA-64)Motorola
1 0
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1 2
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9 2080 RISCCPU MIPSR2000/R3000HPPA-RISC SunMicrosystemsSPARC209064RISCCPU IBM/Motorola PowerPCMIPSR4000/R8000SunMicrosystemsSuperSPACR/UltraSPARCIIDEC AlphaHPPA-RISC7200 RISC CISC CISC x86 RISC x86 21 CPU UltraSPARCIIIIBM POWER4/POWER5/POWER6IntelPentium4/Xeon/Itanium/Core2/Corei3/i5/i7/i9 AMDAthlon/Opteron RISC CISCCISC RISC RISCCPURISC CISCCPU x86 μop CISC 6502(CISC) ARM RISCARMRISC—– RISCCPU [35] 1.1.5 G=109=1000000000109
2 16GB(1.2 1.2
G 3GHz(CPU) ) G=230=1073741824 10 Kkilo210 1024Kkilo103mmilli10−
3 Mmega220 1048576Mmega106μmicro10−
6 Ggiga230 1073741824Ggiga109nnano10−
9 Ttera240 1099511627776Ttera1012ppico10−12 Ppeta250 1125899906842624Ppeta1015ffemto10−15 Eexa260 1152921504606846976Eexa1018aatto10−18 Zzetta270 1180591620717411303424Zzetta1021zzepto10−21 Yyotta2801208925819614629174706176Yyotta1024yyocto10−24 (HalfWord)32 (Byte8) 16 (Word)32 (LongWord)64 x86 16 8086 16G 16GB Bit Binarydigit “ ” “” 10 1.2 CPU(Microprocessors)—– CPUCache(
1 CPU CPUCPU )TLB( I/O(Processors)—–CPUCPUCPU CPU) 1.2.1RISCCPU CPU 1.2 RISCCPU CPU clk clkPCALU 1.2ALU(ArithmeticLogicUnit) PC RISCCPU (RegisterFile)PC(ProgramCounter) (Multiplexer) Load ALU LoadStore Store ALU ( ) PC 1.2
4 (32 CPU CPU CPU 1.3 11
4 )1.2 RISCCPU(Stage) ALUPC IF ID EXE MEM WB 1.3 RISCCPU 5ID(InstructionDecode)(Memoryess)
(5)
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(3)EXE(Execution)
(4) WB(WriteBack) CPU
(2)MEM
5 1980essMemory) CPU Cache CacheCache 1.4Cache Cache DRAM(DynamicRandomCPU di do (DRAM)a CPU dido aCachedi doaCache do diCPU inst dapc 1.4CPU Cache Cache 12
1 (MainMemory) SRAM(StaticRAM)SRAM 1.2.2 CPU CPU CPU CPU (Superscalar)CPU 1.2 ( ) CPU CPU ILP(InstructionLevelParallelism) CPU (Multithreading)CPU CPU 1.5 PC0 RF0 PC1 RF1 FUs PC2Cache RF2 PC3 RF3 DRAMDRAM CPU20% RF0 RF1 Cache RF2 RF3 1.5 CPU 1.5 PC RF FU(FunctionalUnit) ALUFPU(FloatingPointUnit) CPU Cache CPU TLP(ThreadLevelParallelism) CPU (Multi-Core)CPU (Core) CPU1 CPU 1.6 Cache CPU (Multiprocessors) Chip-Multiprocessors CPU
1 CPU CPU 1.2 13 PC0
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1 (VirtualMemory) 2(Process)
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2 1.8 TLB I/O (Bus) I/O / CPU I/OI/O I/O1.9 CPU 1.3 15 CPU / / USB I/O I/O I/O CD-ROM I/O I/O I/O CPUCPU I/O 1.3 1.9I/OI/O Load/StoreI/O CPU I/Ox86 I/Oinout I/OCPU 1.3.1 I(Instructions) T=I×CPI×TPC CPI(CyclesPerInstruction)TPC(TimesPerCycle) 16
1 CPI CPITPCCPIIPC CPI 1/n CPU CISC RISC CPI IPC(InstructionsPerCycle) ITPC TPC Amdahl’sLawn r CPU II IPC S=Pn=To=To=1PoTnTo×r/n+To×(1−r)r/n+(1−r) PnPo 1/(1−r) r=50%
S nr TnTo n→∞
S 21.10 Amdahl’sLaw 1.3.2 S(%) 1009080706050403020100
1 r=99% r=98% r=96%r=90% 10 100 n 1.10Amdahl’sLaw 1000 (Trace-DrivenSimulation) 10000 1.3( BenchmarkWorkload (a) Cache BenchmarkWorkload (b)1.11 ILP) ( (Execution-DrivenSimulation) ( ) Benchmark ) 1.11(b) 17(Benchmark)) 1.11(a) Cache() Benchmark ( 18
1 1.3.3 Systems)CPU/ CPU (Multiprocessors) (ParallelSystems) (puters) (GridComputing) ( ) (InterconnectionNetworks) CPU ( 1.12 (puters) (Servers)(CloudComputing) (Distributed ) CPU CPU CPU 1.12 500 CPU 1%100(CPU 90%CPUIntelAMDx86 x86CPU Amdahl’sLaw CPU 1.10r=99% ) 1.4 (HardwareDescriptionLanguages) CPU 50010%RISCRISCCPU 1.4 19 enable VerilogHDLVHDL
V IEEE VerilogVerilogHDL (Verilog VerifyingLogic) VerilogHDL
4 timecounterverilog.v .v (module) enableclk mycounter4 reg( )
1 clk always posedge <= = CJava moduletime_counter_verilog(enable,inputenable,clk;output[3:0]my_counter;reg[3:0]my_counter;always@(posedgeclk)beginif(enable)my_counter<=my_counterend endmodule clk,my_counter);+4’h1; 1.13mycounter clk Alteraenable1 QuartusIIWebEditionenable0 HDL 1.13 VHDLVerilogHDLC timecountervhdl.vhdVHDLC++ LIBRARYieee;USEieee.std_logic_1164.all; Verilog 20
1 ENTITYtime_counter_vhdlIS PORT( clk :INSTD_LOGIC; enable :INSTD_LOGIC; my_counter:OUTINTEGERRANGE0TO15 ); ENDtime_counter_vhdl; ARCHITECTUREtOFtime_counter_vhdlIS BEGIN PROCESS(clk) t:INTEGERRANGE0TO15; BEGIN IF(clk’EVENTANDclk=’1’)THEN IFenable=’1’THEN cnt:=t+1; ENDIF; ENDIF; my_counter<=t; ENDPROCESS; ENDt; AlteraD AHDLDFF timecounterahdl.tdf SUBDESIGNtime_counter_ahdl( enable,clk :INPUT; my_counter[3..0]:OUTPUT; ) VARIABLE counter[3..0]:DFF; BEGIN counter[].clk=clk; my_counter[]=counter[].q; IFenableTHEN counter[]=counter[]+1; ELSE counter[]=counter[]; ENDIF; END; AlteraQuartusII VHDL VHDLAHDL HDL (Gates) CPUI/O AHDL1.13 VerilogHDLVerilogHDL AlteraVerilog