Iris™PlusGraphicsandUHDGraphicsOpenSource Programmer'sReferenceManual Forthe2017-2019IntelCore™Processors,Pentium®GoldProcessors,Celeron®Processors,andXeon®Processorsbasedonthe"CoffeeLake"PlatformVolume1:Configurations January2020,Revision1.0 CreativeCommonsLicense YouarefreetoShare-tocopy,distribute,display,andperformtheworkunderthefollowingconditions: •Attribution.Youmustattributetheworkinthemannerspecifiedbytheauthororlicensor(butnotinanywaythatsuggeststhattheyendorseyouoryouruseofthework). •NoDerivativeWorks.Youmaynotalter,transform,orbuilduponthiswork. NoticesandDisclaimers INFORMATIONINTHISDOCUMENTISPROVIDEDINCONNECTIONWITHINTEL®PRODUCTS.NOLICENSE,EXPRESSORIMPLIED,BYESTOPPELOROTHERWISE,TOANYINTELLECTUALPROPERTYRIGHTSISGRANTEDBYTHISDOCUMENT.EXCEPTASPROVIDEDININTEL'STERMSANDCONDITIONSOFSALEFORSUCHPRODUCTS,INTELASSUMESNOLIABILITYWHATSOEVERANDINTELDISCLAIMSANYEXPRESSORIMPLIEDWARRANTY,RELATINGTOSALEAND/ORUSEOFINTELPRODUCTSINCLUDINGLIABILITYORWARRANTIESRELATINGTOFITNESSFORAPARTICULARPURPOSE,MERCHANTABILITY,ORINFRINGEMENTOFANYPATENT,COPYRIGHTOROTHERINTELLECTUALPROPERTYRIGHT. A"MissionCriticalApplication"isanyapplicationinwhichfailureoftheIntelProductcouldresult,directlyorindirectly,inpersonalinjuryordeath.SHOULDYOUPURCHASEORUSEINTEL'SPRODUCTSFORANYSUCHMISSIONCRITICALAPPLICATION,YOUSHALLINDEMNIFYANDHOLDINTELANDITSSUBSIDIARIES,SUBCONTRACTORSANDAFFILIATES,ANDTHEDIRECTORS,OFFICERS,ANDEMPLOYEESOFEACH,HARMLESSAGAINSTALLCLAIMSCOSTS,DAMAGES,ANDEXPENSESANDREASONABLEATTORNEYS'FEESARISINGOUTOF,DIRECTLYORINDIRECTLY,ANYCLAIMOFPRODUCTLIABILITY,PERSONALINJURY,ORDEATHARISINGINANYWAYOUTOFSUCHMISSIONCRITICALAPPLICATION,WHETHERORNOTINTELORITSSUBCONTRACTORWASNEGLIGENTINTHEDESIGN,MANUFACTURE,ORWARNINGOFTHEINTELPRODUCTORANYOFITSPARTS. Intelmaymakechangestospecificationsandproductdescriptionsatanytime,withoutnotice.Designersmustnotrelyontheabsenceorcharacteristicsofanyfeaturesorinstructionsmarked"reserved"or"undefined".Intelreservestheseforfuturedefinitionandshallhavenoresponsibilitywhatsoeverforconflictsorpatibilitiesarisingfromfuturechangestothem.Theinformationhereissubjecttochangewithoutnotice.Donotfinalizeadesignwiththisinformation. Theproductsdescribedinthisdocumentmaycontaindesigndefectsorerrorsknownaserratawhichmaycausetheproducttodeviatefrompublishedspecifications.Currentcharacterizederrataareavailableonrequest. ImplementationsoftheI2Cbus/protocolmayrequirelicensesfromvariousentities,includingPhilipsElectronicsN.V.andNorthAmericanPhilipsCorporation. IntelandtheIntellogoaretrademarksofIntelCorporationintheU.S.andothercountries. *Othernamesandbrandsmaybeclaimedasthepropertyofothers. Copyright©2020,IntelCorporation.Allrightsreserved. ii DocRef#IHD-OS-CFL-Vol1-1.20 TableofContents ConfigurationsOverview..................................................................................................................................1
TopLevelBlockDiagramsCFL...................................................................................................................2
DeviceAttributesCFL....................................................................................................................................6
SteppingsandDeviceIDsCFL

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10 DocRef#IHD-OS-CFL-Vol1-1.20 iii ConfigurationsOverview TheIntel"Gen"GraphicsArchitecturewasfirstintroducedtothemarketin2004.Sincethattime,thearchitectureandimplementationhaveevolvedtoaddmanynewfeatures,increaseperformance,andimprovepowerefficiency. Eachproductgenerationhasitsownconfigurationschapter.Eachchapterhasasectionforeachproject,andeachprojectcontainsthefollowingsubsections: •TopLevelBlockDiagrams-Showsbasicfeatureblocksoftheproject’sgraphicsarchitecture,forGTconfigurations. •DeviceAttributes-Listsdetailsofthegraphicsconfigurationoptionsforeachproject.•SteppingsandDeviceIDs-ListsallthecurrentuniqueGTDie/Packagesforaspecificproject. DocRef#IHD-OS-CFL-Vol1-1.20
1 TopLevelBlockDiagramsCFL ThediagramsbelowshowbasicfeatureblocksoftheGen9CoffeeLake(CFL)graphicsarchitecture.GT2Configuration TheGT2configurationcontainsoneUnsliceandoneSlicewithseparatepowerdomainsforeach,althoughtheyshareasingleclockdomain. GT3Configuration TheGT3configurationhasanidenticalUnslicetoGT2,exceptthatitcontainstwoSlices.SeparateclockdomainsfortheUnsliceandSlicemaybeavailabledependingonSKU.TheL3cachesofeachbinetoprovideanaggregateL3cacheoftwicethesizeandtwicethebandwidthofasingleinstance.GT3alsohasadditionalmediablockswithsecondinstanceofVEBoxandVDBoxeach.
2 DocRef#IHD-OS-CFL-Vol1-1.20 Thisdiagramisbasedonthefollowingfunctionalpartitions:(a)GeometryFixedFunctions(Geom/FF)(b)MediaFixedFunctions(Media/FF)(c)GlobalAssetsandGTInterface(GA)(d)OneormoreSubslices(threeshown)(e)ASliceCommonblock(f)AnL3Cache(L3$)block Notethatbinationof(a),(b),and(c)istypicallyreferredtoasthe“unslice”,whilebinationof(d),(e),and(f)isreferredtoaspute“slice”.Thefunctionalityineachofthesegroupingsisfurtherbrokendownasfollows: •Unslice–Fixedfunctionpipelinesfor3D,GPGPU,andMediaoperations,andinterfacetotheoutsideworld.oThe3DGeometry/FixedFunction(Geom/FF)blockconsistingof:▪3Dfixedfunctionpipeline(CS,VFVS,HS,TE,DS,GS,SOL,SL,SFE,SVG) DocRef#IHD-OS-CFL-Vol1-1.20
3 ▪VideoFront-Endunit(VFE)▪ThreadSpawnerunit(TSG)andtheglobalThreadDispatcherunit(TDG)▪UnifiedReturnBufferManager(URBM)oMediafixedfunctionassets:▪VideoDecode(VD)Box▪VideoEncode(VE)Box▪WirelessDisplay(WD)BOX▪Scaler&FormatConverter(SFC)oTheGlobalAssets(GA)blockastheprimaryinterfaceandmemorystreamgatewaytotheoutsideworld,consistingof:▪GTInterface(GTI)▪StateVariableManager(SVM)▪Blitter(BLT)▪GraphicsArbiter(GAM)•Subslice(threeshown)–puteunitwithsupportingfixed-orshared-functionassetssufficientfortheEUcapability.oAbankofExecutionUnits(EUs)–eightpersubsliceshownoSampler,supportingbothmediaand3DfunctionsoGateway(GWY)oInstructioncache(IC)oLocalThreadDispatcher(TDL)oBarycentricCalculator(BC)oPixelShaderDispatcher(PSD)oDataCluster(HDC)oDataportRenderCache(DAPRC)-twopersubslice•SliceCommon–Scalablefixedfunctionassetswhichsupportputehorsepowerprovidedtwoormoresubslices.o3DFixedFunction:▪Windower/Maskunit(WM)▪Hi-Z(HZ)andIntermediateZ(IZ)▪SetupBackend(SBE)▪RCPFE,BE▪3Dstreamcaches(RCC,MSC,STC,RCZ)oMediaFixedFunctions:▪DAPRSC▪SVL
4 DocRef#IHD-OS-CFL-Vol1-1.20 ▪TDC•L3Cache–backingL3cacheforcertainmemorystreamsemanatingfromsubslices. oL3Datacachewithsupportfordata,URB,andsharedlocalmemory(SLM) DocRef#IHD-OS-CFL-Vol1-1.20
5 DeviceAttributesCFL ThefollowingtablelistsdetailedGTdeviceattributesforproposedCoffeeLake(CFL)SKUs.NOTE:Thisinformationispreliminary,andsubjecttochange. ProductFamilyArchitecturalName*SKUName SlicecountSubsliceCountEU/SubsliceEUcount(total)ThreadCountThreadCount(Total)FLOPs/Clk-HalfPrecision,MAD(peak)FLOPs/Clk-SinglePrecision,MAD(peak)FLOPs/Clk-DoublePrecision,MAD(peak)Unsliceclocking(coupled/decoupledfromCrslice)GTI/RingInterfacesGTIbandwidth(bytes/unslice-clk) eDRAMSupportGraphicsVirtualAddressRangeGraphicsPhysicalAddressRange L3Cache,totalsize(bytes)L3Cache,bankcountL3Cache,bandwidth(bytes/clk) L3Cache,D$Size(Kbytes)URBSize(kbytes)SLMSize(kbytes)LLC/L4size(bytes)[1] ProductConfigurationAttributeTable CFL 1x2x6 1x3x8 GT1F GT2 GlobalAttributes
1 1
2 3
6 8 12 23/24[b]
7 7 84 161/168 384 736/768 192 368/384 48 92/96 coupled coupled
1 1 64:
R 64:
R 64:
W 64:
W N/A N/A 48bit 48bit 39bit 39bit Caches&DedicatedMemories 384K 768K
2 4 2x64:R2x64:
W 4x64:R4x64:
W 192K-256K 512K 128K-192K 384K 0,128K 0,192K ~2MB/CPUcore ~2MB/CPUcore 2x3x8GT3 26847/48[b]7329/3361504/1536 752/768 188/192 coupled 164:R64:W0,64MB48bit39bit 1536K8 8x64:R8x64:W1024K 768K0,384K~2MB/CPUcore
6 DocRef#IHD-OS-CFL-Vol1-1.20 InstructionCache(IC,bytes)ColorCache(RCC,bytes)MSCCache(MSC,bytes)HiZCache(HZC,bytes)ZCache(RCZ,bytes)StencilCache(STC,bytes) FMAD,SP(ops/EU/clk)FMUL,SP(ops/EU/clk)FADD,SP(ops/EU/clk)MIN,MAX,SP(ops/EU/clk)CMP,SP(ops/EU/clk)INV,SP(ops/EU/clk)SQRT,SP(ops/EU/clk)RSQRT,SP(ops/EU/clk)LOG,SP(ops/EU/clk)EXP,SP(ops/EU/clk)POW,SP(ops/EU/clk)IDIV,SP(ops/EU/clk)TRIG,SP(ops/EU/clk)FDIV,SP(ops/EU/clk) DataPorts(HDC)L3Load/Store(dwords/clk)SLMLoad/Store(dwords/clk)AtomicInc,32b-sequentialaddresses(dwords/clk)AtomicInc,32b-sameaddress(dwords/clk)AtomicCmpWr,32b-sequentialaddresses(dwords/clk)AtomicCmpWr,32b-sameaddress(dwords/clk) GeometrypipesSamplers(3D)TexelRate,point,32b(tex/clk) ProductConfigurationAttributeTable 2x48K 3x48K 24K 24K 16K 16K 12K 12K 32K 32K 8K 8K InstructionIssueRates
8 8
8 8
8 8
8 8
8 8
2 2
2 2
2 2
2 2
2 2
1 1 1-
6 1-
6 2
2 1
1 Load/Store
2 3 2x
64 3x64 2x64 3x64 2x64 3x64 2x4 3x4 2x32 3x32 2x4 3x4 3DAttributes
1 1
2 3
8 12 DocRef#IHD-OS-CFL-Vol1-1.20 6x48K2x24K2x16K2x12K2x32K2x8K 888882222211-621 66x646x646x64 6x4 6x32 6x4 1624
7 TexelRate,point,64b(tex/clk) TexelRate,point,128b(tex/clk) TexelRate,bilinear,32b(tex/clk)TexelRate,bilinear,64b(tex/clk) TexelRate,bilinear,128b(tex/clk) TexelRate,trilinear,32b(tex/clk) TexelRate,trilinear,64b(tex/clk)TexelRate,trilinear,128b(tex/clk) TexelRate,aniso2x,MIPLinear,,32b(tex/clk) TexelRate,aniso4x,MIPLinear,,32b(tex/clk) TexelRate,aniso8x,MIPLinear,,32b(tex/clk)TexelRate,aniso16x,MIPLinear,,32b(tex/clk) HiZRate,(ppc) IZRate,(ppc)StencilRate(ppc) (500MHz,DDR-2400oreDRAM;Rangedependsonpressionratio)PixelRate,fill,32bpp(pix/clk,RCChit) PixelRate,fill,32bpp(pix/clk,LLChit@1.0xunsliceclk)[2]PixelRate,fill,32bpp(pix/clk,LLChit,@1.5xunsliceclk)[2] PixelRate,fill,32bpp(pix/clk,memory,@1.0xunsliceclk)[2] PixelRate,fill,32bpp(pix/clk,memory,@1.5xunsliceclk)[2] (500MHz,DDR-2400oreDRAM;Rangedependsonpressionratio) PixelRate,blend,32bpp(p/clk,RCChit)PixelRate,blend,32bpp(p/clk,LLChit,@1.0xunsliceclk)[2] ProductConfigurationAttributeTable
8 12
8 12
8 12
8 12
2 3
8 12
4 6
1 1.5
2 3
1 1.5 0.5 0.75 0.25 0.375 64 64 16 16 64 64
8 8 N/A N/A N/A N/A
8 8 24
242424624123631.50.752x642x162x64 16 16
8 DocRef#IHD-OS-CFL-Vol1-1.20 ProductConfigurationAttributeTable PixelRate,blend,32bpp(p/clk, N/A N/A LLChit,@1.5xunsliceclk)[2] PixelRate,blend,32bpp(pix/clk,memory,@1.0xunsliceclk)[2] PixelRate,blend,32bpp(pix/clk, N/A N/A memory,@1.5xunsliceclk)[2] MediaAttributes Samplers(media)
2 3
6 VDBoxInstances
1 1
2 VEBoxInstances
1 1
2 SFCInstances
1 1
1 WGBoxInstances N/A N/A N/A DisplayAttributes DisplayPipes
3 3
3 DisplayPlanesperPipe
3 3
3 DDIports
2 2
2 eDPports
1 1
1 Footnotes:*ArchitecturalName=SliceCountxSubsliceCountxEUsperSubslice[a]SKUnaming&detailshasnotyetbeendecided.[b]OneEUreservedfordierecoverypurposes.[c]IntheGT4SKU,adecoupledunslicefeatureissupported,wherethesliceandunslicemayoperateonindependentvoltageplanes(ifsupportedbytheplatform),andmayhaveindependentclocking. DocRef#IHD-OS-CFL-Vol1-1.20
9 SteppingsandDeviceIDsCFL ThefollowingtablelistscurrentlyproposedvariationsofGTDie/PackagesforGen9CoffeeLake(CFL). Thisinformationispreliminary,andsubjecttochangeatanytime. SegmentSKU DID2 CPUBrandGFX CPU GT/Display DID28thRev TDPEUsBrand # NameStepping VersionGroupingGenIDPORNotes MobileU43eR15 48Corei7645Intel® D0 KBLI0/KBLC0
1 Iris®Plus Graphics 3EA60x0YRecycleforCFLU43eR MobileU43eR15 MobileU43e 28 MobileU43e 28 MobileU43e 28 MobileU2f2f 15 48Corei5645Intel® D0 Iris®Plus Graphics 47Corei3655Intel® D0 Iris®Plus Graphics 48Corei5655Intel® D0 Iris®Plus Graphics 48Corei7655Intel® D0 Iris®Plus Graphics 23Corei3620Intel® D0 UHD Graphics KBLI0/KBLC0
1 KBLI0/KBLC0
3 KBLI0/KBLC0
4 KBLI0/KBLC0
4 KBLI0/KBLC020 3EA60x0YRecycleforCFLU43eR 3EA80x0Y 3EA50x03EA50x03EA90x0 YRecycleforCFLU43eR YRecycleforCFLU43eR YRecoverySKUs basedonU43e MobileU42f 15 24Corei5620Intel® D0 KBLI0/KBLC0 20 3EA90x0YRecovery UHD SKUs Graphics basedon U43e MobileU42f 15 24Corei7620Intel® D0 KBLI0/KBLC0 20 3EA90x0YRecovery UHD SKUs Graphics basedon U43e MobileH4f2 35 23Corei3630Intel® U0CFLA0/KBLC05 UHD Graphics MobileH4f2 45 23Corei5630Intel® U0CFLA0/KBLC05 UHD Graphics Mobile/IOTGH4f2 45 24Corei5630Intel® U0CFLA0/KBLC05 UHD Graphics Mobile/IOTGH6245/6524Corei7630Intel® U0CFLA0/KBLC05 UHD Graphics 3E9B0x0Y3E9B0x0Y3E9B0x0Y3E9B0x0Y 10 DocRef#IHD-OS-CFL-Vol1-1.20 SegmentSKUMobile/IOTGH2f1f Mobile/IOTGH2f1f Mobile H82 Mobile H82 MobileH6f2 TDP45/65 45/65 45/6545/6545/65 CPUEUsBrand Brand# GFXName CPUStepping GT/DisplayVersion DID2DID28thRevGroupingGenIDPOR 12Pentium610Intel® U0CFLA0/KBLC015 UHD Graphics 3E9C0x0Y 12Celeron610Intel® U0CFLA0/KBLC015 UHD Graphics 3E9C0x0Y 24Corei9630Intel® P0 CFLB0/KBLC0
5 UHD Graphics 24Corei9630Intel® R0 CFLC0/KBLC0
5 UHD Graphics 24Corei7630Intel® U0CFLA0/KBLC05 UHD Graphics 3E9B0x1Y3E9B0x2Y3E9B0x0Y Notes Fuseddown6cores SKUs Fuseddown6cores SKUs S2f1f35/6512Celeron610Intel® B0 KBLF0/KBLC0
6 UHD Graphics S2f1f35/6512Pentium610Intel® B0 KBLF0/KBLC0
6 UHD Graphics /IOTGS4235/65/9523Corei3630Intel® B0 KBLF0/KBLC0
7 UHD Graphics S2f235/6523Pentium630Intel® B0 KBLF0/KBLC0
7 UHD Graphics S2f1f35/6512Pentium610Intel® U0CFLA0/KBLC08 UHD Graphics S6235/6523Corei5630Intel® U0CFLA0/KBLC09 UHD Graphics /IOTGS6235/65/9524Corei5630Intel® U0CFLA0/KBLC09 UHD Graphics /IOTGS6235/65/9524Corei7630Intel® U0CFLA0/KBLC09 UHD Graphics 3E930x0Y3E930x0Y3E910x0Y3E910x0Y3E900x0Y3E920x0Y3E920x0Y3E920x0Y MobileWSH62 45 24MobileP630Intel® U0CFLA0/KBLC010 Xeon UHD Graphics MobileWSH8245/6524MobileP630Intel® P0CFLB0/KBLC010 Xeon UHD Graphics 3E940x0Y3E940x1Y DocRef#IHD-OS-CFL-Vol1-1.20 11 SegmentSKU DID2 CPUBrandGFX CPU GT/Display DID28thRev TDPEUsBrand # NameStepping VersionGroupingGenIDPORNotes MobileWSH8245/6524MobileP630Intel® R0CFLC0/KBLC010 Xeon UHD Graphics 3E940x2Y WSS6265/80/9524XeonP630Intel® U0CFLA0/KBLC011 UHD Graphics 3E960x0Y WSS4f265/71/8324XeonP630Intel® U0CFLA0/KBLC011 UHD Graphics 3E960x0Y WSWS S82S82S6f2S6f2S6f1fS4f1fS2f1fS82S6f2S82S82S6f2S6f2 95/65/3595/65/3595/65/35 65/3565/3565/3565/3595/8095/8095/65/3595/65/3595/65/3565/35 24Corei924Corei724Corei523Corei512Corei712Corei312Pentium24Xeon24Xeon24Corei924Corei724Corei523Corei5 630630630630610610610P630P630630630630630 Intel®UHDGraphics Intel®UHDGraphics Intel®UHDGraphics Intel®UHDGraphics Intel®UHDGraphics Intel®UHDGraphics Intel®UHDGraphics Intel®UHDGraphics Intel®UHDGraphics Intel®UHDGraphics Intel®UHDGraphics Intel®UHDGraphics Intel®UHDGraphics P0CFLB0/KBLC012P0CFLB0/KBLC012P0CFLB0/KBLC012P0CFLB0/KBLC012P0CFLB0/KBLC013P0CFLB0/KBLC013P0CFLB0/KBLC013P0CFLB0/KBLC014P0CFLB0/KBLC014R0CFLC0/KBLC012R0CFLC0/KBLC012R0CFLC0/KBLC012R0CFLC0/KBLC012 3E980x1Y3E980x1Y3E980x1Y3E980x1Y3E990x1Y3E990x1Y3E990x1Y3E9A0x1Y3E9A0x1Y3E980x2Y3E980x2Y3E980x2Y3E980x2Y 12 DocRef#IHD-OS-CFL-Vol1-1.20 Segment SKUS6f1f S4f1f S2f1f WSS82 WSS6f2 TDP65/3565/3565/3595/8095/80 CPUEUsBrand Brand# GFXName CPUStepping GT/DisplayVersion DID2DID28thRevGroupingGenIDPOR 12Corei7610Intel® R0CFLC0/KBLC013 UHD Graphics 3E990x2Y 12Corei3610Intel® R0CFLC0/KBLC013 UHD Graphics 3E990x2Y 12Pentium610Intel® R0CFLC0/KBLC013 UHD Graphics 3E990x2Y 24XeonP630Intel®UHD Graphics R0CFLC0/KBLC014 3E9A0x2Y 24XeonP630Intel®UHD Graphics R0CFLC0/KBLC014 3E9A0x2Y Notes Note- **CFLGTbaseline=KBLRG0,with4additionalECOsonA0stepping,and1additionalECOon4+3eofA0stepping. **DespiteCFL4+3eissupersetofCFL6+2andKBL-R,butinbug_deHSDthefixesforCFL4+3earemarkedasKBLI0,anditalsodoesnothavetheHWchangestosupport6cores.HencenotbeingcalledasCFLB0steppingbutKBLI0toalignwithbugdatabase. DocRef#IHD-OS-CFL-Vol1-1.20 13